Searched refs:VGPR (Results 1 – 18 of 18) sorted by relevance
| /external/llvm/lib/Target/AMDGPU/ |
| D | SIRegisterInfo.td | 73 // VGPR registers
75 def VGPR#Index : SIReg <"VGPR"#Index, Index> {
133 // VGPR 32-bit registers
135 (add (sequence "VGPR%u", 0, 255))>;
137 // VGPR 64-bit registers
142 // VGPR 96-bit registers
148 // VGPR 128-bit registers
155 // VGPR 256-bit registers
166 // VGPR 512-bit registers
282 // VSrc_* Operands with an SGPR, VGPR or a 32-bit immediate
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| D | SIIntrinsics.td | 27 llvm_anyint_ty, // vdata(VGPR), overloaded for types i32, v2i32, v4i32
29 llvm_i32_ty, // vaddr(VGPR)
43 [llvm_anyint_ty], // vdata(VGPR), overloaded for types i32, v2i32, v4i32
45 llvm_anyint_ty, // vaddr(VGPR)
59 [llvm_v4f32_ty], // vdata(VGPR)
60 [llvm_anyint_ty, // vaddr(VGPR)
75 [llvm_v4f32_ty], // vdata(VGPR)
76 [llvm_anyint_ty, // vaddr(VGPR)
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| D | SIMachineFunctionInfo.h | 107 unsigned VGPR; member
109 SpilledReg(unsigned R, int L) : VGPR (R), Lane (L) { } in SpilledReg()
110 SpilledReg() : VGPR(0), Lane(-1) { } in SpilledReg()
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| D | SIRegisterInfo.cpp | 285 if (Spill.VGPR == AMDGPU::NoRegister) { in eliminateFrameIndex()
292 Spill.VGPR) in eliminateFrameIndex()
318 if (Spill.VGPR == AMDGPU::NoRegister) { in eliminateFrameIndex()
326 .addReg(Spill.VGPR) in eliminateFrameIndex()
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| D | SIMachineFunctionInfo.cpp | 169 Spill.VGPR = LaneVGPRs[LaneVGPRIdx]; in getSpilledReg()
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| D | SIInstrInfo.td | 104 SDTCisVT<1, iAny>, // vdata(VGPR)
106 SDTCisVT<3, i32>, // vaddr(VGPR)
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| D | SIInstructions.td | 2752 // Offset in an 32Bit VGPR
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | SIGenRegisterInfo.pl | 134 my @VGPR;
137 $VGPR[$i] = "VGPR$i";
221 for (my $i = 0; $i <= $#VGPR; $i++) {
222 push (@{$hw_values{$i}}, $VGPR[$i]);
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| /external/clang/test/SemaOpenCL/ |
| D | amdgpu-num-register-attrs.cl | 20 // Check 0 VGPR is accepted.
26 // Check both 0 SGPR and VGPR is accepted.
29 // Too large VGPR value.
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| /external/llvm/test/CodeGen/AMDGPU/ |
| D | add_i64.ll | 20 ; Check that the SGPR add operand is correctly moved to a VGPR.
31 ; Swap the arguments. Check that the SGPR -> VGPR copy works with the
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| D | sgpr-copy-duplicate-operand.ll | 4 ; Copy VGPR -> SGPR used twice as an instruction operand, which is then
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| D | add.ll | 142 ; %0 will be stored in a VGPR, so the comiler will be forced to copy %a
143 ; to a VGPR before doing the add.
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| D | si-lod-bias.ll | 4 ; This shader has the potential to generated illegal VGPR to SGPR copies if
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| D | local-atomics.ll | 31 ; XXX - Is it really necessary to load 4 into VGPR?
327 ; XXX - Is it really necessary to load 4 into VGPR?
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| D | and.ll | 63 ; Second use is a VGPR use of the constant.
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| D | salu-to-valu.ll | 19 ; Make sure we aren't using VGPR's for the srsrc operand of BUFFER_LOAD_*
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| D | sgpr-copy.ll | 4 ; This test checks that no VGPR to SGPR copies are created by the register
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| /external/llvm/docs/ |
| D | LangRef.rst | 3297 - ``[0-9]v``: The 32-bit VGPR register, number 0-9.
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