Searched refs:VOPC (Results 1 – 10 of 10) sorted by relevance
| /external/llvm/docs/ |
| D | AMDGPUUsage.rst | 78 VOP1, VOP2, VOP3, VOPC Instructions
84 VOP1, VOP2, and VOPC instructions based on the operands. If you want to force
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIDefines.h | 31 VOPC = 1 << 13, enumerator
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| D | SIInstrFormats.td | 33 field bits<1> VOPC = 0;
65 let TSFlags{13} = VOPC;
107 let VOPC = 1;
605 class VOPC <bits<8> op, dag ins, string asm, list<dag> pattern> :
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| D | SIInstrInfo.h | 235 return MI.getDesc().TSFlags & SIInstrFlags::VOPC; in isVOPC()
239 return get(Opcode).TSFlags & SIInstrFlags::VOPC; in isVOPC()
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| D | SISchedule.td | 39 // instructions and have VALU rates, but write to the SALU (i.e. VOPC
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| D | SIInstrInfo.td | 1234 // VOPC instructions are a special case because for the 32-bit
1772 def _si : VOPC<op.SI, ins, asm, []>,
1782 def _vi : VOPC<op.VI, ins, asm, []>,
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| D | SIInstructions.td | 521 // VOPC Instructions
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| /external/mesa3d/src/gallium/drivers/radeon/MCTargetDesc/ |
| D | SIMCCodeEmitter.cpp | 52 VOPC = 15 enumerator
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | SIInstrInfo.td | 428 class VOPC <bits<8> op, dag ins, string asm, list<dag> pattern> :
439 let EncodingType = 15; //SIInstrEncodingType::VOPC
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| D | SIInstrFormats.td | 102 VOPC <
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