Searched refs:VPTR (Results 1 – 9 of 9) sorted by relevance
/external/llvm/test/CodeGen/AMDGPU/ |
D | 32-bit-local-address-space.ll | 25 ; SI: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[SPTR]] 26 ; SI: ds_read_b32 [[VPTR]] 36 ; SI: v_mov_b32_e32 [[VPTR:v[0-9]+]], s{{[0-9]+}} 37 ; SI: ds_read_b32 v{{[0-9]+}}, [[VPTR]] offset:4 49 ; SI: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[SPTR]] 50 ; SI: ds_read_b32 [[VPTR]] 121 ; SI: v_mov_b32_e32 [[VPTR:v[0-9]+]], s{{[0-9]+}} 123 ; SI: ds_write_b32 [[VPTR]], [[VAL]] offset:4 133 ; SI: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[SPTR]] 134 ; SI: ds_write_b32 [[VPTR]], v{{[0-9]+$}}
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D | atomic_cmp_swap_local.ll | 11 ; GCN-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]] 13 ; GCN: ds_cmpst_rtn_b32 [[RESULT:v[0-9]+]], [[VPTR]], [[VCMP]], [[VSWAP]] offset:16 30 ; GCN-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]] 33 ; GCN: ds_cmpst_rtn_b64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[VPTR]], v{{\[}}[[LOVCMP]]:[[HIVCMP]]{{\]}}… 64 ; GCN-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]] 66 ; GCN: ds_cmpst_b32 [[VPTR]], [[VCMP]], [[VSWAP]] offset:16 82 ; GCN-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]] 85 ; GCN: ds_cmpst_b64 [[VPTR]], v{{\[}}[[LOVCMP]]:[[HIVCMP]]{{\]}}, v{{\[}}[[LOSWAPV]]:[[HISWAPV]]{{\…
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D | ds_write2st64.ll | 7 ; SI-DAG: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 2, v{{[0-9]+}} 8 ; SI: ds_write2st64_b32 [[VPTR]], [[VAL]], [[VAL]] offset1:1 25 ; SI-DAG: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 2, v{{[0-9]+}} 26 ; SI: ds_write2st64_b32 [[VPTR]], [[VAL0]], [[VAL1]] offset0:2 offset1:5 46 ; SI-DAG: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 2, v{{[0-9]+}} 47 ; SI: ds_write2st64_b32 [[VPTR]], [[VAL0]], [[VAL1]] offset1:255 66 ; SI-DAG: v_add_i32_e32 [[VPTR:v[0-9]+]], 67 ; SI: ds_write2st64_b64 [[VPTR]], [[VAL0]], [[VAL1]] offset0:4 offset1:127
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D | ds_write2.ll | 9 ; SI-DAG: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 2, v{{[0-9]+}} 10 ; SI: ds_write2_b32 [[VPTR]], [[VAL]], [[VAL]] offset1:8 27 ; SI-DAG: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 2, v{{[0-9]+}} 28 ; SI: ds_write2_b32 [[VPTR]], [[VAL0]], [[VAL1]] offset1:8 86 ; SI: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 2, v{{[0-9]+}} 87 ; SI: ds_write2_b32 [[VPTR]], v[[VAL0]], v[[VAL1]] offset1:8 107 ; SI-DAG: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 2, v{{[0-9]+}} 108 ; SI: ds_write2_b32 [[VPTR]], v[[VAL0]], v[[VAL1]] offset1:8 126 ; SI-DAG: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 2, v{{[0-9]+}} 127 ; SI: ds_write2_b32 [[VPTR]], v[[VAL0]], v[[VAL1]] offset1:8 [all …]
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D | local-atomics64.ll | 37 ; GCN-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]] 38 ; GCN: ds_add_rtn_u64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[VPTR]], v{{\[}}[[LOVDATA]]:[[HIVDATA]]{{\]}}… 51 ; GCN: ds_inc_rtn_u64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[VPTR]], v{{\[}}[[LOVDATA]]:[[HIVDATA]]{{\]}} 92 ; GCN: ds_dec_rtn_u64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[VPTR]], v{{\[}}[[LOVDATA]]:[[HIVDATA]]{{\]}} 282 ; GCN: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]] 283 ; GCN: ds_add_u64 [[VPTR]], v{{\[}}[[LOVDATA]]:[[HIVDATA]]{{\]}} offset:32 294 ; GCN: ds_inc_u64 [[VPTR]], v{{\[}}[[LOVDATA]]:[[HIVDATA]]{{\]}} 330 ; GCN: ds_dec_u64 [[VPTR]], v{{\[}}[[LOVDATA]]:[[HIVDATA]]{{\]}}
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D | local-atomics.ll | 10 ; GCN: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[SPTR]] 11 ; GCN: ds_wrxchg_rtn_b32 [[RESULT:v[0-9]+]], [[VPTR]], [[DATA]] 36 ; GCN: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[SPTR]] 37 ; GCN: ds_add_rtn_u32 [[RESULT:v[0-9]+]], [[VPTR]], [[DATA]] 310 ; GCN: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[SPTR]] 311 ; GCN: ds_wrxchg_rtn_b32 [[RESULT:v[0-9]+]], [[VPTR]], [[DATA]] 331 ; GCN: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[SPTR]] 332 ; GCN: ds_add_u32 [[VPTR]], [[DATA]]
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D | ds_read2.ll | 313 ; SI: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 3, {{v[0-9]+}} 314 ; SI: ds_read2_b64 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, [[VPTR]] offset1:8
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/external/llvm/test/CodeGen/Mips/llvm-ir/ |
D | extractelement.ll | 17 ; ALL-DAG: addiu [[VPTR:\$[0-9]+]], $sp, 6 18 ; ALL-DAG: addu [[EPTR:\$[0-9]+]], $4, [[VPTR]]
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/external/clang/lib/CodeGen/ |
D | CGDebugInfo.cpp | 1441 llvm::DIType *VPTR = DBuilder.createMemberType( in CollectVTableInfo() local 1444 EltTys.push_back(VPTR); in CollectVTableInfo()
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