Searched refs:VREG (Results 1 – 9 of 9) sorted by relevance
/external/llvm/test/CodeGen/AMDGPU/ |
D | llvm.AMDGPU.bfe.i32.ll | 88 ; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0 89 ; SI: buffer_store_dword [[VREG]], 183 ; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0 184 ; SI: buffer_store_dword [[VREG]], 195 ; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0 196 ; SI: buffer_store_dword [[VREG]], 207 ; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0 208 ; SI: buffer_store_dword [[VREG]], 219 ; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], -1 220 ; SI: buffer_store_dword [[VREG]], [all …]
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D | llvm.AMDGPU.bfe.u32.ll | 195 ; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0 196 ; SI: buffer_store_dword [[VREG]], 331 ; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0 332 ; SI: buffer_store_dword [[VREG]], 343 ; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0 344 ; SI: buffer_store_dword [[VREG]], 355 ; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0 356 ; SI: buffer_store_dword [[VREG]], 367 ; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 1 368 ; SI: buffer_store_dword [[VREG]], [all …]
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D | trunc-store-i1.ll | 8 ; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], [[SREG]] 9 ; SI: buffer_store_byte [[VREG]], 27 ; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], [[SREG]] 28 ; SI: buffer_store_byte [[VREG]],
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D | llvm.AMDGPU.umax.ll | 26 ; SI: buffer_load_ubyte [[VREG:v[0-9]+]], 27 ; SI: v_max_u32_e32 [[RESULT:v[0-9]+]], 0, [[VREG]]
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D | llvm.AMDGPU.umin.ll | 26 ; SI: buffer_load_ubyte [[VREG:v[0-9]+]], 27 ; SI: v_min_u32_e32 [[RESULT:v[0-9]+]], 0, [[VREG]]
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/external/llvm/test/CodeGen/PowerPC/ |
D | ppc32-pic.ll | 21 ; SMALL-BSS-DAG: lwz [[VREG:[0-9]+]], bar@GOT(30) 22 ; SMALL-BSS-DAG: lwz {{[0-9]+}}, 0([[VREG]])
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D | ppc32-pic-large.ll | 24 ; LARGE-BSS-DAG: lwz [[VREG:[0-9]+]], [[VREF:\.LC[0-9]+]]-.LTOC(30) 25 ; LARGE-BSS-DAG: lwz {{[0-9]+}}, 0([[VREG]])
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/external/llvm/test/CodeGen/SystemZ/ |
D | vec-args-05.ll | 23 ; CHECK-STACK-DAG: vl [[VREG:%v[0-9]+]], 0([[REG1]]) 24 ; CHECK-STACK-DAG: vst [[VREG]], 160(%r15)
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/external/vixl/src/vixl/a64/ |
D | assembler-a64.cc | 199 #define VREG(n) v##n, macro 201 REGISTER_CODE_LIST(VREG) 203 #undef VREG
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