Searched refs:XAssisted (Results 1 – 15 of 15) sorted by relevance
| /external/valgrind/VEX/priv/ |
| D | host_tilegx_defs.c | 313 showTILEGXCondCode(instr->GXin.XAssisted.cond)); in ppTILEGXInstr()
315 ppHRegTILEGX(instr->GXin.XAssisted.dstGA); in ppTILEGXInstr()
317 ppTILEGXAMode(instr->GXin.XAssisted.amPC); in ppTILEGXInstr()
319 (Int)instr->GXin.XAssisted.jk); in ppTILEGXInstr()
860 i->GXin.XAssisted.dstGA = dstGA; in TILEGXInstr_XAssisted()
861 i->GXin.XAssisted.amPC = amPC; in TILEGXInstr_XAssisted()
862 i->GXin.XAssisted.cond = cond; in TILEGXInstr_XAssisted()
863 i->GXin.XAssisted.jk = jk; in TILEGXInstr_XAssisted()
1041 addHRegUse(u, HRmRead, i->GXin.XAssisted.dstGA); in getRegUsage_TILEGXInstr()
1042 addRegUsage_TILEGXAMode(u, i->GXin.XAssisted.amPC); in getRegUsage_TILEGXInstr()
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| D | host_amd64_defs.c | 713 i->Ain.XAssisted.dstGA = dstGA; in AMD64Instr_XAssisted()
714 i->Ain.XAssisted.amRIP = amRIP; in AMD64Instr_XAssisted()
715 i->Ain.XAssisted.cond = cond; in AMD64Instr_XAssisted()
716 i->Ain.XAssisted.jk = jk; in AMD64Instr_XAssisted()
1133 showAMD64CondCode(i->Ain.XAssisted.cond)); in ppAMD64Instr()
1135 ppHRegAMD64(i->Ain.XAssisted.dstGA); in ppAMD64Instr()
1137 ppAMD64AMode(i->Ain.XAssisted.amRIP); in ppAMD64Instr()
1139 (Int)i->Ain.XAssisted.jk); in ppAMD64Instr()
1523 addHRegUse(u, HRmRead, i->Ain.XAssisted.dstGA); in getRegUsage_AMD64Instr()
1524 addRegUsage_AMD64AMode(u, i->Ain.XAssisted.amRIP); in getRegUsage_AMD64Instr()
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| D | host_x86_defs.c | 675 i->Xin.XAssisted.dstGA = dstGA; in X86Instr_XAssisted()
676 i->Xin.XAssisted.amEIP = amEIP; in X86Instr_XAssisted()
677 i->Xin.XAssisted.cond = cond; in X86Instr_XAssisted()
678 i->Xin.XAssisted.jk = jk; in X86Instr_XAssisted()
1015 showX86CondCode(i->Xin.XAssisted.cond)); in ppX86Instr()
1017 ppHRegX86(i->Xin.XAssisted.dstGA); in ppX86Instr()
1019 ppX86AMode(i->Xin.XAssisted.amEIP); in ppX86Instr()
1021 (Int)i->Xin.XAssisted.jk); in ppX86Instr()
1333 addHRegUse(u, HRmRead, i->Xin.XAssisted.dstGA); in getRegUsage_X86Instr()
1334 addRegUsage_X86AMode(u, i->Xin.XAssisted.amEIP); in getRegUsage_X86Instr()
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| D | host_mips_defs.c | 931 i->Min.XAssisted.dstGA = dstGA; in MIPSInstr_XAssisted()
932 i->Min.XAssisted.amPC = amPC; in MIPSInstr_XAssisted()
933 i->Min.XAssisted.cond = cond; in MIPSInstr_XAssisted()
934 i->Min.XAssisted.jk = jk; in MIPSInstr_XAssisted()
1339 showMIPSCondCode(i->Min.XAssisted.cond)); in ppMIPSInstr()
1341 ppHRegMIPS(i->Min.XAssisted.dstGA, mode64); in ppMIPSInstr()
1343 ppMIPSAMode(i->Min.XAssisted.amPC, mode64); in ppMIPSInstr()
1345 (Int)i->Min.XAssisted.jk); in ppMIPSInstr()
1694 addHRegUse(u, HRmRead, i->Min.XAssisted.dstGA); in getRegUsage_MIPSInstr()
1695 addRegUsage_MIPSAMode(u, i->Min.XAssisted.amPC); in getRegUsage_MIPSInstr()
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| D | host_arm_defs.c | 1203 i->ARMin.XAssisted.dstGA = dstGA; in ARMInstr_XAssisted()
1204 i->ARMin.XAssisted.amR15T = amR15T; in ARMInstr_XAssisted()
1205 i->ARMin.XAssisted.cond = cond; in ARMInstr_XAssisted()
1206 i->ARMin.XAssisted.jk = jk; in ARMInstr_XAssisted()
1668 showARMCondCode(i->ARMin.XAssisted.cond)); in ppARMInstr()
1670 ppHRegARM(i->ARMin.XAssisted.dstGA); in ppARMInstr()
1672 ppARMAMode1(i->ARMin.XAssisted.amR15T); in ppARMInstr()
1674 (Int)i->ARMin.XAssisted.jk); in ppARMInstr()
2086 addHRegUse(u, HRmRead, i->ARMin.XAssisted.dstGA); in getRegUsage_ARMInstr()
2087 addRegUsage_ARMAMode1(u, i->ARMin.XAssisted.amR15T); in getRegUsage_ARMInstr()
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| D | host_arm64_defs.c | 943 i->ARM64in.XAssisted.dstGA = dstGA; in ARM64Instr_XAssisted()
944 i->ARM64in.XAssisted.amPC = amPC; in ARM64Instr_XAssisted()
945 i->ARM64in.XAssisted.cond = cond; in ARM64Instr_XAssisted()
946 i->ARM64in.XAssisted.jk = jk; in ARM64Instr_XAssisted()
1495 showARM64CondCode(i->ARM64in.XAssisted.cond)); in ppARM64Instr()
1497 ppHRegARM64(i->ARM64in.XAssisted.dstGA); in ppARM64Instr()
1499 ppARM64AMode(i->ARM64in.XAssisted.amPC); in ppARM64Instr()
1501 (Int)i->ARM64in.XAssisted.jk); in ppARM64Instr()
1988 addHRegUse(u, HRmRead, i->ARM64in.XAssisted.dstGA); in getRegUsage_ARM64Instr()
1989 addRegUsage_ARM64AMode(u, i->ARM64in.XAssisted.amPC); in getRegUsage_ARM64Instr()
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| D | host_ppc_defs.c | 829 i->Pin.XAssisted.dstGA = dstGA; in PPCInstr_XAssisted()
830 i->Pin.XAssisted.amCIA = amCIA; in PPCInstr_XAssisted()
831 i->Pin.XAssisted.cond = cond; in PPCInstr_XAssisted()
832 i->Pin.XAssisted.jk = jk; in PPCInstr_XAssisted()
1609 showPPCCondCode(i->Pin.XAssisted.cond)); in ppPPCInstr()
1611 ppHRegPPC(i->Pin.XAssisted.dstGA); in ppPPCInstr()
1613 ppPPCAMode(i->Pin.XAssisted.amCIA); in ppPPCInstr()
1616 (Int)i->Pin.XAssisted.jk); in ppPPCInstr()
2329 addHRegUse(u, HRmRead, i->Pin.XAssisted.dstGA); in getRegUsage_PPCInstr()
2330 addRegUsage_PPCAMode(u, i->Pin.XAssisted.amCIA); in getRegUsage_PPCInstr()
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| D | host_tilegx_defs.h | 436 } XAssisted; member
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| D | host_x86_defs.h | 481 } XAssisted; member
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| D | host_amd64_defs.h | 502 } XAssisted; member
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| D | host_mips_defs.h | 477 } XAssisted; member
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| D | host_arm_defs.h | 718 } XAssisted; member
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| D | host_arm64_defs.h | 626 } XAssisted; member
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| D | host_ppc_defs.h | 642 } XAssisted; member
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| /external/valgrind/docs/internals/ |
| D | t-chaining-notes.txt | 75 control-transfer instructions: XDirect, XIndir and XAssisted.
112 * new instructions in backends: XDirect, XIndir and XAssisted.
120 XAssisted is used for "assisted" (do something first, then jump)
126 all transfers must be done with XAssisted. In such cases the
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