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Searched refs:ZEROReg (Results 1 – 3 of 3) sorted by relevance

/external/llvm/lib/Target/Mips/
DMips32r6InstrInfo.td774 multiclass Cmp_Pats<ValueType VT, Instruction NOROp, Register ZEROReg> {
776 (NOROp (!cast<Instruction>("CMP_UEQ_"#NAME) VT:$lhs, VT:$rhs), ZEROReg)>;
778 (NOROp (!cast<Instruction>("CMP_UN_"#NAME) VT:$lhs, VT:$rhs), ZEROReg)>;
780 (NOROp (!cast<Instruction>("CMP_EQ_"#NAME) VT:$lhs, VT:$rhs), ZEROReg)>;
792 (NOROp (!cast<Instruction>("CMP_EQ_"#NAME) VT:$lhs, VT:$rhs), ZEROReg)>;
DMipsSEInstrInfo.cpp457 unsigned ZEROReg = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO; in loadImmediate() local
476 BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(ZEROReg) in loadImmediate()
DMipsInstrInfo.td2151 Instruction SLTiuOp, Register ZEROReg> {
2153 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>;
2155 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>;
2176 (BNEOp RC:$cond, ZEROReg, bb:$dst)>;
2188 Instruction SLTuOp, Register ZEROReg> {
2192 (SLTuOp ZEROReg, RC:$lhs)>;
2196 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>;