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Searched refs:areMemAccessesTriviallyDisjoint (Results 1 – 10 of 10) sorted by relevance

/external/llvm/lib/Target/AArch64/
DAArch64InstrInfo.h56 areMemAccessesTriviallyDisjoint(MachineInstr *MIa, MachineInstr *MIb,
DAArch64LoadStoreOptimizer.cpp853 return !TII->areMemAccessesTriviallyDisjoint(MIa, MIb); in mayAlias()
DAArch64InstrInfo.cpp615 AArch64InstrInfo::areMemAccessesTriviallyDisjoint(MachineInstr *MIa, in areMemAccessesTriviallyDisjoint() function in AArch64InstrInfo
/external/llvm/lib/Target/Hexagon/
DHexagonInstrInfo.h249 bool areMemAccessesTriviallyDisjoint(MachineInstr *MIa, MachineInstr *MIb,
DHexagonExpandCondsets.cpp856 if (HII->areMemAccessesTriviallyDisjoint(TheI, ToI)) in canMoveMemTo()
DHexagonInstrInfo.cpp1391 bool HexagonInstrInfo::areMemAccessesTriviallyDisjoint(MachineInstr *MIa, in areMemAccessesTriviallyDisjoint() function in HexagonInstrInfo
/external/llvm/lib/Target/AMDGPU/
DSIInstrInfo.h136 bool areMemAccessesTriviallyDisjoint(
DSIInstrInfo.cpp1200 bool SIInstrInfo::areMemAccessesTriviallyDisjoint(MachineInstr *MIa, in areMemAccessesTriviallyDisjoint() function in SIInstrInfo
/external/llvm/include/llvm/Target/
DTargetInstrInfo.h1352 areMemAccessesTriviallyDisjoint(MachineInstr *MIa, MachineInstr *MIb,
/external/llvm/lib/CodeGen/
DScheduleDAGInstrs.cpp580 if (TII->areMemAccessesTriviallyDisjoint(MIa, MIb, AA)) in MIsNeedChainEdge()