Home
last modified time | relevance | path

Searched refs:asr (Results 1 – 25 of 172) sorted by relevance

1234567

/external/valgrind/none/tests/arm/
Dv6intThumb.stdout.exp2153 adds.w r1, r2, r3, asr #0 :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000…
2154 adds.w r1, r2, r3, asr #1 :: rd 0x44cd64bb rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000…
2155 adds.w r1, r2, r3, asr #15 :: rd 0x3141a757 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000…
2156 adds.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000…
2165 add.w r1, r2, r3, asr #0 :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000…
2166 add.w r1, r2, r3, asr #1 :: rd 0x44cd64bb rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000…
2167 add.w r1, r2, r3, asr #15 :: rd 0x3141a757 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000…
2168 add.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000…
2177 adds.w r1, r2, r3, asr #0 :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x80000000…
2178 adds.w r1, r2, r3, asr #1 :: rd 0xfccd64bb rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x80000000…
[all …]
/external/llvm/test/CodeGen/X86/
Datomic-dagsched.ll15 %asr.iv6 = phi i8* [ %29, %test.exit ], [ %scevgep, %entry ]
35 %asr.iv9 = phi i8* [ %scevgep10, %vector_kernel_entry.i ], [ %asr.iv6, %dim_0_vector_pre_head.i ]
36 …%asr.iv = phi i64 [ %asr.iv.next, %vector_kernel_entry.i ], [ %vector.size.i, %dim_0_vector_pre_he…
38 %asr.iv911 = addrspacecast i8* %asr.iv9 to <8 x i32> addrspace(1)*
39 %9 = load <8 x i32>, <8 x i32> addrspace(1)* %asr.iv911, align 4
56 store <8 x i32> %vectorvector_func.i, <8 x i32> addrspace(1)* %asr.iv911, align 4
57 %asr.iv.next = add i64 %asr.iv, -1
58 %scevgep10 = getelementptr i8, i8* %asr.iv9, i64 32
59 %dim_0_vector_cmp.to.max.i = icmp eq i64 %asr.iv.next, 0
75 %asr.iv12 = phi i64 [ %asr.iv.next13, %scalar_kernel_entry.i ], [ %22, %dim_0_pre_head.i ]
[all …]
/external/llvm/test/MC/ARM/
Darm-shift-encoding.s8 ldr r0, [r0, r0, asr #32]
9 ldr r0, [r0, r0, asr #16]
18 @ CHECK: ldr r0, [r0, r0, asr #32] @ encoding: [0x40,0x00,0x90,0xe7]
19 @ CHECK: ldr r0, [r0, r0, asr #16] @ encoding: [0x40,0x08,0x90,0xe7]
28 pld [r0, r0, asr #32]
29 pld [r0, r0, asr #16]
38 @ CHECK: [r0, r0, asr #32] @ encoding: [0x40,0xf0,0xd0,0xf7]
39 @ CHECK: [r0, r0, asr #16] @ encoding: [0x40,0xf8,0xd0,0xf7]
48 str r0, [r0, r0, asr #32]
49 str r0, [r0, r0, asr #16]
[all …]
Dthumb-shift-encoding.s12 sbc.w r5, r4, r11, asr #32
13 sbc.w r6, r3, r12, asr #16
22 @ CHECK: sbc.w r5, r4, r11, asr #32 @ encoding: [0x64,0xeb,0x2b,0x05]
23 @ CHECK: sbc.w r6, r3, r12, asr #16 @ encoding: [0x63,0xeb,0x2c,0x46]
32 and.w r5, r4, r11, asr #32
33 and.w r6, r3, r12, asr #16
42 @ CHECK: and.w r5, r4, r11, asr #32 @ encoding: [0x04,0xea,0x2b,0x05]
43 @ CHECK: and.w r6, r3, r12, asr #16 @ encoding: [0x03,0xea,0x2c,0x46]
Dbasic-arm-instructions.s75 adc r4, r5, r6, asr #1
76 adc r4, r5, r6, asr #31
77 adc r4, r5, r6, asr #32
84 adc r6, r7, r8, asr r9
95 adc r4, r5, asr #1
96 adc r4, r5, asr #31
97 adc r4, r5, asr #32
103 adc r6, r7, asr r9
114 @ CHECK: adc r4, r5, r6, asr #1 @ encoding: [0xc6,0x40,0xa5,0xe0]
115 @ CHECK: adc r4, r5, r6, asr #31 @ encoding: [0xc6,0x4f,0xa5,0xe0]
[all …]
/external/llvm/test/MC/AArch64/
Darm64-logical-encoding.s56 and w1, w2, w3, asr #2
57 and x1, x2, x3, asr #2
67 ; CHECK: and w1, w2, w3, asr #2 ; encoding: [0x41,0x08,0x83,0x0a]
68 ; CHECK: and x1, x2, x3, asr #2 ; encoding: [0x41,0x08,0x83,0x8a]
78 ands w1, w2, w3, asr #2
79 ands x1, x2, x3, asr #2
89 ; CHECK: ands w1, w2, w3, asr #2 ; encoding: [0x41,0x08,0x83,0x6a]
90 ; CHECK: ands x1, x2, x3, asr #2 ; encoding: [0x41,0x08,0x83,0xea]
100 bic w1, w2, w3, asr #3
101 bic x1, x2, x3, asr #3
[all …]
Dbasic-a64-diagnostics.s185 add x4, sp, x9, asr #5
201 add w1, w2, w3, asr #-1
202 add w1, w2, w3, asr #32
207 add x1, x2, x3, asr #-1
208 add x1, x2, x3, asr #64
250 adds w1, w2, w3, asr #-1
251 adds w1, w2, w3, asr #32
256 adds x1, x2, x3, asr #-1
257 adds x1, x2, x3, asr #64
299 sub w1, w2, w3, asr #-1
[all …]
/external/libvpx/libvpx/vp8/common/arm/armv6/
Diwalsh_v6.asm71 asr r12, r3, #19 ; [0]
73 asr lr, r2, #19 ; [1]
77 asr r2, r2, #3 ; [2]
79 asr r3, r3, #3 ; [3]
82 asr r12, r5, #19 ; [4]
84 asr lr, r4, #19 ; [5]
88 asr r4, r4, #3 ; [6]
90 asr r5, r5, #3 ; [7]
108 asr r12, r7, #19 ; [8]
110 asr lr, r6, #19 ; [9]
[all …]
Ddequant_idct_v6.asm110 pkhtb r6, r6, r8, asr #16
115 pkhtb r8, r7, r9, asr #16
137 mov r8, r7, asr #3
138 pkhtb r9, r8, r10, asr #19
139 mov r8, r1, asr #3
140 pkhtb r8, r8, r6, asr #19
153 mov r7, r7, asr #3
154 pkhtb r7, r7, r10, asr #19
155 mov r1, r1, asr #3
156 pkhtb r1, r1, r6, asr #19
/external/compiler-rt/lib/builtins/arm/
Ddivmodsi4.S59 eor ip, r0, r0, asr #31
60 eor lr, r1, r1, asr #31
61 sub r0, ip, r0, asr #31
62 sub r1, lr, r1, asr #31
67 eor r0, r0, r4, asr #31
68 eor r1, r1, r5, asr #31
69 sub r0, r0, r4, asr #31
70 sub r1, r1, r5, asr #31
Dmodsi3.S52 eor r2, r0, r0, asr #31
53 eor r3, r1, r1, asr #31
54 sub r0, r2, r0, asr #31
55 sub r1, r3, r1, asr #31
59 eor r0, r0, r4, asr #31
60 sub r0, r0, r4, asr #31
Ddivsi3.S54 eor r2, r0, r0, asr #31
55 eor r3, r1, r1, asr #31
56 sub r0, r2, r0, asr #31
57 sub r1, r3, r1, asr #31
61 eor r0, r0, r4, asr #31
62 sub r0, r0, r4, asr #31
Dcomparesf2.S80 mvnlo r0, r1, asr #31
87 movhi r0, r1, asr #31
122 mvnlo r0, r1, asr #31
124 movhi r0, r1, asr #31
/external/llvm/test/CodeGen/Hexagon/intrinsics/
Dxtype_shift.ll8 declare i64 @llvm.hexagon.S2.asr.i.p(i64, i32)
10 %z = call i64 @llvm.hexagon.S2.asr.i.p(i64 %a, i32 0)
13 ; CHECK: = asr({{.*}}, #0)
29 declare i32 @llvm.hexagon.S2.asr.i.r(i32, i32)
31 %z = call i32 @llvm.hexagon.S2.asr.i.r(i32 %a, i32 0)
34 ; CHECK: = asr({{.*}}, #0)
51 declare i64 @llvm.hexagon.S2.asr.i.p.nac(i64, i64, i32)
53 %z = call i64 @llvm.hexagon.S2.asr.i.p.nac(i64 %a, i64 %b, i32 0)
56 ; CHECK: -= asr({{.*}}, #0)
72 declare i64 @llvm.hexagon.S2.asr.i.p.acc(i64, i64, i32)
[all …]
/external/llvm/test/MC/Disassembler/Hexagon/
Dxtype_shift.txt6 # CHECK: r17:16 = asr(r21:20, #31)
12 # CHECK: r17 = asr(r21, #31)
20 # CHECK: r17:16 -= asr(r21:20, #31)
26 # CHECK: r17:16 += asr(r21:20, #31)
32 # CHECK: r17 -= asr(r21, #31)
38 # CHECK: r17 += asr(r21, #31)
58 # CHECK: r17:16 &= asr(r21:20, #31)
64 # CHECK: r17:16 |= asr(r21:20, #31)
74 # CHECK: r17 &= asr(r21, #31)
80 # CHECK: r17 |= asr(r21, #31)
[all …]
/external/libvpx/libvpx/vp8/encoder/arm/armv6/
Dwalsh_v6.asm77 mov r2, r2, asr #3 ; >> 3
83 mov r0, r0, asr #3 ; >> 3
90 mov r2, r2, asr #3 ; >> 3
97 mov r0, r0, asr #3 ; >> 3
114 mov r2, r2, asr #3 ; >> 3
120 mov r9, r9, asr #3 ; >> 3
126 mov r2, r2, asr #3 ; >> 3
133 mov r9, r9, asr #3 ; >> 3
149 mov r2, r2, asr #3 ; >> 3
155 mov r9, r9, asr #3 ; >> 3
[all …]
Dvp8_short_fdct4x4_armv6.asm148 asr r2, r2, #4 ; scale top halfword
150 asr r3, r3, #4 ; scale top halfword
151 pkhtb r4, r2, r8, asr #20 ; pack and scale bottom halfword
152 pkhtb r5, r3, r9, asr #20 ; pack and scale bottom halfword
175 pkhtb r9, r9, r8, asr #16
182 pkhtb r5, r5, r4, asr #16 ; [o13|o12]
202 asr r2, r2, #4 ; scale top halfword
204 asr r3, r3, #4 ; scale top halfword
205 pkhtb r4, r2, r8, asr #20 ; pack and scale bottom halfword
206 pkhtb r5, r3, r9, asr #20 ; pack and scale bottom halfword
[all …]
/external/llvm/test/CodeGen/AArch64/
Dsdivpow2.ll9 ; CHECK: asr w0, w8, #3
19 ; CHECK: neg w0, w8, asr #3
29 ; CHECK: asr w0, w8, #5
39 ; CHECK: asr x0, x8, #3
49 ; CHECK: neg x0, x8, asr #3
59 ; CHECK: asr x0, x8, #6
70 ; CHECK: asr x0, x8, #48
Dfast-isel-sdiv.ll6 ; CHECK: asr {{w[0-9]+}}, w0, #3
16 ; CHECK-NEXT: asr {{w[0-9]+}}, [[REG2]], #3
26 ; CHECK-NEXT: neg {{w[0-9]+}}, [[REG2]], asr #3
33 ; CHECK: asr {{x[0-9]+}}, x0, #4
43 ; CHECK-NEXT: asr {{x[0-9]+}}, [[REG2]], #4
53 ; CHECK-NEXT: neg {{x[0-9]+}}, [[REG2]], asr #4
Daddsub-shifted.ll140 ; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, asr #18
145 ; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, asr #31
150 ; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, asr #5
156 ; CHECK-NOT: sub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, asr #19
161 ; CHECK: neg {{w[0-9]+}}, {{w[0-9]+}}, asr #15
166 ; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, asr #18
171 ; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, asr #31
176 ; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, asr #5
182 ; CHECK-NOT: sub {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, asr #19
187 ; CHECK: neg {{x[0-9]+}}, {{x[0-9]+}}, asr #45
[all …]
/external/llvm/test/MC/Disassembler/AArch64/
Darm64-logical.txt66 # CHECK: and w1, w2, w3, asr #2
67 # CHECK: and x1, x2, x3, asr #2
88 # CHECK: ands w1, w2, w3, asr #2
89 # CHECK: ands x1, x2, x3, asr #2
110 # CHECK: bic w1, w2, w3, asr #3
111 # CHECK: bic x1, x2, x3, asr #3
132 # CHECK: bics w1, w2, w3, asr #3
133 # CHECK: bics x1, x2, x3, asr #3
154 # CHECK: eon w1, w2, w3, asr #4
155 # CHECK: eon x1, x2, x3, asr #4
[all …]
/external/llvm/test/CodeGen/ARM/
Dpack.ll41 ; CHECK: pkhtb r0, r0, r1, asr #16
51 ; CHECK: pkhtb r0, r0, r1, asr #16
61 ; CHECK: pkhtb r0, r0, r1, asr #12
72 ; CHECK: pkhtb r0, r0, r1, asr #18
85 ; CHECK-NOT: pkhtb r0, r0, r1, asr #22
94 ; CHECK: pkhtb r0, r0, r1, asr #16
104 ; CHECK: pkhtb r0, r0, r1, asr #17
Dthumb2-size-opt.ll13 define i32 @asr-imm(i32 %a) nounwind readnone {
14 ; CHECK-LABEL: "asr-imm":
15 ; CHECK: asr.w r{{[0-9]+}}, r{{[0-9]+}}, #13 @ encoding: [{{0x..,0x..,0x..,0x..}}]
22 define i32 @asr-reg(i32 %a, i32 %b) nounwind readnone {
23 ; CHECK-LABEL: "asr-reg":
24 ; CHECK: asr.w r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}} @ encoding: [{{0x..,0x..,0x..,0x..}}]
/external/llvm/test/CodeGen/Thumb2/
Dthumb2-pack.ll50 ; CHECK: pkhtb r0, r0, r1, asr #16
60 ; CHECK: pkhtb r0, r0, r1, asr #16
70 ; CHECK: pkhtb r0, r0, r1, asr #12
81 ; CHECK: pkhtb r0, r0, r1, asr #18
91 ; CHECK-NOT: pkhtb r0, r0, r1, asr #22
103 ; CHECK: pkhtb r0, r0, r1, asr #16
113 ; CHECK: pkhtb r0, r0, r1, asr #22
/external/llvm/test/CodeGen/Hexagon/
Dbit-eval.ll10 %0 = tail call i32 @llvm.hexagon.S2.asr.i.r.rnd(i32 2147483647, i32 0)
18 %0 = tail call i32 @llvm.hexagon.S2.asr.i.r.rnd.goodsyntax(i32 2147483647, i32 1)
46 declare i32 @llvm.hexagon.S2.asr.i.r.rnd(i32, i32) #0
47 declare i32 @llvm.hexagon.S2.asr.i.r.rnd.goodsyntax(i32, i32) #0

1234567