| /external/webrtc/webrtc/common_audio/signal_processing/ |
| D | signal_processing_unittest.cc | 94 int16_t b16 = -17; in TEST_F() local
119 EXPECT_EQ(104, WebRtcSpl_AddSatW16(a16, b16)); in TEST_F()
120 EXPECT_EQ(138, WebRtcSpl_SubSatW16(a16, b16)); in TEST_F()
162 int16_t b16[kVectorSize]; in TEST_F() local
168 WebRtcSpl_MemSetW16(b16, 3, kVectorSize); in TEST_F()
170 EXPECT_EQ(3, b16[kk]); in TEST_F()
172 WebRtcSpl_ZerosArrayW16(b16, kVectorSize); in TEST_F()
174 EXPECT_EQ(0, b16[kk]); in TEST_F()
188 WEBRTC_SPL_MEMCPY_W16(b16, bTmp16, kVectorSize); in TEST_F()
190 EXPECT_EQ(b16[kk], bTmp16[kk]); in TEST_F()
[all …]
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| /external/llvm/test/CodeGen/NVPTX/ |
| D | pr13291-i1-store.ll | 16 ; PTX32: and.b16 %rs{{[0-9]+}}, %rs{{[0-9]+}}, 1;
17 ; PTX32: setp.eq.b16 %p{{[0-9]+}}, %rs{{[0-9]+}}, 1;
19 ; PTX64: and.b16 %rs{{[0-9]+}}, %rs{{[0-9]+}}, 1;
20 ; PTX64: setp.eq.b16 %p{{[0-9]+}}, %rs{{[0-9]+}}, 1;
|
| D | arithmetic-int.ll | 251 ; CHECK: and.b16 %rs{{[0-9]+}}, %rs{{[0-9]+}}, %rs{{[0-9]+}}
258 ; CHECK: or.b16 %rs{{[0-9]+}}, %rs{{[0-9]+}}, %rs{{[0-9]+}}
265 ; CHECK: xor.b16 %rs{{[0-9]+}}, %rs{{[0-9]+}}, %rs{{[0-9]+}}
273 ; CHECK: shl.b16 %rs{{[0-9]+}}, %rs{{[0-9]+}}, %r{{[0-9]+}}
|
| /external/llvm/test/MC/Mips/ |
| D | micromips-16-bit-instructions.s | 58 # CHECK-EL: b16 132 # encoding: [0x42,0xcc]
60 # CHECK-EL: b16 132 # encoding: [0x42,0xcc]
113 # CHECK-EB: b16 132 # encoding: [0xcc,0x42]
115 # CHECK-EB: b16 132 # encoding: [0xcc,0x42]
163 b16 132
|
| D | micromips-branch-fixup.s | 18 # CHECK-FIXUP: b16 bar # encoding: [A,0b110011AA]
82 b16 bar
|
| /external/llvm/test/CodeGen/Mips/Fast-ISel/ |
| D | bswap1.ll | 16 define void @b16() {
17 ; ALL-LABEL: b16:
|
| /external/clang/test/CodeGen/ |
| D | arm64-be-bitfield.c | 5 struct bt3 { signed b2:10; signed b3:10; } b16; variable
|
| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXIntrinsics.td | 776 !strconcat(".reg .b16 %temp;\n\t",
778 !strconcat("mov.b16 \t$dst, %temp;\n",
782 !strconcat(".reg .b16 %temp;\n\t",
784 !strconcat("mov.b16 \t$dst, %temp;\n",
789 !strconcat(".reg .b16 %temp;\n\t",
790 !strconcat("mov.b16 \t%temp, $src0;\n\t",
1656 "mov.b16 \t$r, $s;",
3322 "suld.b.1d.b16.clamp \\{$r\\}, [$s, \\{$x\\}];",
3343 "suld.b.a1d.b16.clamp \\{$r\\}, [$s, \\{$l, $x\\}];",
3364 "suld.b.2d.b16.clamp \\{$r\\}, [$s, \\{$x, $y\\}];",
[all …]
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| D | NVPTXVector.td | 341 def ShiftLV2I16 : VecShiftOp<V2AsmStr<"shl.b16">, shl, V2I16Regs, V2I32Regs,
343 def ShiftLV4I16 : VecShiftOp<V4AsmStr<"shl.b16">, shl, V4I16Regs, V4I32Regs,
345 def ShiftLV2I8 : VecShiftOp<V2AsmStr<"shl.b16">, shl, V2I8Regs, V2I32Regs,
347 def ShiftLV4I8 : VecShiftOp<V4AsmStr<"shl.b16">, shl, V4I8Regs, V4I32Regs,
936 def V4I16_Select : Vec_Select<V4I16Regs, Select_Str4<"b16">.s, SELECTi16rr>;
937 def V2I16_Select : Vec_Select<V2I16Regs, Select_Str2<"b16">.s, SELECTi16rr>;
938 def V4I8_Select : Vec_Select<V4I8Regs, Select_Str4<"b16">.s, SELECTi8rr>;
939 def V2I8_Select : Vec_Select<V2I8Regs, Select_Str2<"b16">.s, SELECTi8rr>;
1122 def LoadParamScalar4I16 : LoadParamScalar4Inst<Int16Regs, ".v4.b16">;
1127 def LoadParamScalar2I16 : LoadParamScalar2Inst<Int32Regs, ".v2.b16">;
[all …]
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| D | NVPTXInstrInfo.td | 976 !strconcat(OpcStr, ".b16 \t$dst, $a, $b;"),
980 !strconcat(OpcStr, ".b16 \t$dst, $a, $b;"),
1006 "not.b16 \t$dst, $src;",
1270 defm SETP_b16 : SETP<"b16", Int16Regs, i16imm>;
1295 defm SET_b16 : SET<"b16", Int16Regs, i16imm>;
1347 defm SELP_b16 : SELP_PATTERN<"b16", Int16Regs, i16imm, imm>;
1889 def LoadParamMemI16 : LoadParamMemInst<Int16Regs, ".b16">;
1893 def LoadParamMemV2I16 : LoadParamV2MemInst<Int16Regs, ".b16">;
1896 def LoadParamMemV4I16 : LoadParamV4MemInst<Int16Regs, ".b16">;
1907 def StoreParamI16 : StoreParamInst<Int16Regs, ".b16">;
[all …]
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| /external/libopus/silk/ |
| D | MacroCount.h | 197 static OPUS_INLINE opus_int64 silk_SMLALBB(opus_int64 a64, opus_int16 b16, opus_int16 c16){ in silk_SMLALBB() argument
200 ret = a64 + ((opus_int64)(b16) * /*(opus_int64)*/(c16)); in silk_SMLALBB()
549 static OPUS_INLINE opus_int16 silk_ADD_SAT16( opus_int16 a16, opus_int16 b16 ) { in silk_ADD_SAT16() argument
552 res = (opus_int16)silk_SAT16( silk_ADD32( (opus_int32)(a16), (b16) ) ); in silk_ADD_SAT16()
577 static OPUS_INLINE opus_int16 silk_SUB_SAT16( opus_int16 a16, opus_int16 b16 ) { in silk_SUB_SAT16() argument
581 res = (opus_int16)silk_SAT16( silk_SUB32( (opus_int32)(a16), (b16) ) ); in silk_SUB_SAT16()
|
| D | MacroDebug.h | 135 static OPUS_INLINE opus_int16 silk_ADD_SAT16_( opus_int16 a16, opus_int16 b16, char *file, int line… in silk_ADD_SAT16_() argument
137 res = (opus_int16)silk_SAT16( silk_ADD32( (opus_int32)(a16), (b16) ) ); in silk_ADD_SAT16_()
138 if ( res != silk_SAT16( (opus_int32)a16 + (opus_int32)b16 ) ) in silk_ADD_SAT16_()
140 fprintf (stderr, "silk_ADD_SAT16(%d, %d) in %s: line %d\n", a16, b16, file, line); in silk_ADD_SAT16_()
196 static OPUS_INLINE opus_int16 silk_SUB_SAT16_( opus_int16 a16, opus_int16 b16, char *file, int line… in silk_SUB_SAT16_() argument
198 res = (opus_int16)silk_SAT16( silk_SUB32( (opus_int32)(a16), (b16) ) ); in silk_SUB_SAT16_()
199 if ( res != silk_SAT16( (opus_int32)a16 - (opus_int32)b16 ) ) in silk_SUB_SAT16_()
201 fprintf (stderr, "silk_SUB_SAT16(%d, %d) in %s: line %d\n", a16, b16, file, line); in silk_SUB_SAT16_()
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| D | SigProc_FIX.h | 411 #define silk_SMLALBB(a64, b16, c16) silk_ADD64((a64),(opus_int64)((opus_int32)(b16) * (opus… argument
427 #define silk_DIV32_16(a32, b16) ((opus_int32)((a32) / (b16))) argument
|
| /external/iptables/include/linux/netfilter/ |
| D | xt_HMARK.h | 33 } b16; member
|
| /external/kernel-headers/original/uapi/linux/netfilter/ |
| D | xt_HMARK.h | 33 } b16; member
|
| /external/clang/test/SemaCXX/ |
| D | uninitialized.cpp | 478 …B* b16 = getPtrB(b16->y); // expected-warning {{variable 'b16' is uninitialized when used within … in setupB() local
510 B* b16 = getPtrB(b16->y); // expected-warning {{variable 'b16' is uninitialized when used within i… variable
1173 B b16 = { {}, {b16.a2.i1} }; // expected-warning{{uninitialized}} variable
1231 B b16 = { {}, {b16.a2.i1} }; // expected-warning{{uninitialized}} member
1260 b16{ {}, {b16.a2.i1} }, // expected-warning{{uninitialized}}
|
| /external/libusb/libusb/ |
| D | libusb.h | 45 uint16_t b16; \
50 _tmp.b16; \
|
| /external/llvm/test/CodeGen/Mips/ |
| D | ra-allocatable.ll | 36 @b16 = external global i32*
150 %33 = load i32*, i32** @b16, align 4
|
| /external/tcpdump/tests/ |
| D | ripv2_auth.out | 31 0x0000: 728c 5b16 9a1b 3913 0021 a73f 7a73 bc1b
|
| /external/valgrind/VEX/priv/ |
| D | host_arm64_defs.c | 4026 UInt b16 = 2; /* impossible */ in emit_ARM64Instr() local
4029 case ARM64fpu_NEG: b16 = 1; b15 = 0; break; in emit_ARM64Instr()
4030 case ARM64fpu_SQRT: b16 = 1; b15 = 1; break; in emit_ARM64Instr()
4031 case ARM64fpu_ABS: b16 = 0; b15 = 1; break; in emit_ARM64Instr()
4034 if (b16 < 2 && b15 < 2) { in emit_ARM64Instr()
4035 *p++ = X_3_8_5_6_5_5(X000, X11110011, (X0000 << 1) | b16, in emit_ARM64Instr()
4064 UInt b16 = 2; /* impossible */ in emit_ARM64Instr() local
4067 case ARM64fpu_NEG: b16 = 1; b15 = 0; break; in emit_ARM64Instr()
4068 case ARM64fpu_SQRT: b16 = 1; b15 = 1; break; in emit_ARM64Instr()
4069 case ARM64fpu_ABS: b16 = 0; b15 = 1; break; in emit_ARM64Instr()
[all …]
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| D | host_x86_isel.c | 1078 HReg b16 = newVRegI(env); in iselIntExpr_R_wrk() local
1089 addInstr(env, mk_iMOVsd_RR(b16s, b16)); in iselIntExpr_R_wrk()
1091 addInstr(env, X86Instr_Sh32(Xsh_SHL, shift, b16)); in iselIntExpr_R_wrk()
1093 addInstr(env, X86Instr_Sh32(shr_op, shift, b16)); in iselIntExpr_R_wrk()
1094 addInstr(env, X86Instr_Alu32R(Xalu_MUL, X86RMI_Reg(a16), b16)); in iselIntExpr_R_wrk()
1095 return b16; in iselIntExpr_R_wrk()
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| /external/llvm/test/MC/Disassembler/Mips/micromips32r3/ |
| D | valid.txt | 45 0xcc 0x42 # CHECK: b16 132
|
| D | valid-el.txt | 45 0x42 0xcc # CHECK: b16 132
|
| /external/v8/test/webkit/ |
| D | dfg-inline-arguments-use-from-uninlined-code-expected.txt | 44 PASS "" + baz("a" + __i, "b" + (__i + 1), "c" + (__i + 2)) is "a15,b16,c17,a15,b16,c17"
|
| /external/v8/test/mjsunit/es6/ |
| D | classes-subclass-builtins.js | 763 this.b16 = 0
|