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/external/libhevc/common/arm64/
Dihevc_intra_pred_luma_vert.s223 bsl v18.8b, v24.8b , v16.8b //only select row values from q12(predpixel)
224 bsl v3.8b, v25.8b , v16.8b
239 bsl v1.8b, v24.8b , v16.8b
240 bsl v6.8b, v25.8b , v16.8b
264 bsl v18.8b, v24.8b , v16.8b //only select row values from q12(predpixel)
265 bsl v3.8b, v25.8b , v16.8b
277 bsl v1.8b, v24.8b , v16.8b
278 bsl v6.8b, v25.8b , v16.8b
294 bsl v18.8b, v24.8b , v16.8b //only select row values from q12(predpixel)
295 bsl v3.8b, v25.8b , v16.8b
[all …]
Dihevc_intra_pred_luma_dc.s251 bsl v19.8b, v29.8b , v2.8b //first row with dst[0]
263 bsl v20.8b, v3.8b , v16.8b //row 1 (prol)
272 bsl v21.8b, v3.8b , v16.8b //row 2 (prol)
280 bsl v20.8b, v3.8b , v16.8b //row 3 (prol)
288 bsl v21.8b, v3.8b , v16.8b //row 4 (prol)
296 bsl v20.8b, v3.8b , v16.8b //row 5 (prol)
305 bsl v21.8b, v3.8b , v16.8b //row 6 (prol)
314 bsl v20.8b, v3.8b , v16.8b //row 7 (prol)
342 bsl v20.8b, v3.8b , v16.8b //row 9 (prol)
485 bsl v19.8b, v29.8b , v2.8b //first row with dst[0]
[all …]
Dihevc_deblk_luma_horz.s542 bsl v18.8b,v24.8b,v14.8b
550 bsl v19.8b,v25.8b,v12.8b
572 bsl v18.8b,v27.8b,v14.8b
576 bsl v19.8b,v26.8b,v13.8b
Dihevc_deblk_luma_vert.s549 bsl v3.8b,v30.8b,v16.8b
561 bsl v16.8b,v2.8b,v22.8b
607 bsl v5.8b,v30.8b,v3.8b
618 bsl v0.8b,v4.8b,v23.8b
/external/llvm/test/CodeGen/AArch64/
Darm64-neon-select_cc.ll10 ; CHECK: bsl [[DUPMASK]].8b, v0.8b, v1.8b
20 ; CHECK-NEXT: bsl [[DUPMASK]].8b, v2.8b, v3.8b
29 ; CHECK-NEXT: bsl v[[MASK]].8b, v2.8b, v3.8b
41 ; CHECK: bsl [[DUPMASK]].16b, v0.16b, v1.16b
51 ; CHECK-NEXT: bsl [[DUPMASK]].16b, v2.16b, v3.16b
61 ; CHECK-NEXT: bsl [[DUPMASK]].16b, v2.16b, v3.16b
73 ; CHECK: bsl [[DUPMASK]].8b, v0.8b, v1.8b
85 ; CHECK: bsl [[DUPMASK]].16b, v0.16b, v1.16b
97 ; CHECK: bsl [[DUPMASK]].8b, v0.8b, v1.8b
109 ; CHECK: bsl [[DUPMASK]].16b, v0.16b, v1.16b
[all …]
Dneon-bitwise-instructions.ll49 ; CHECK: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
58 ; CHECK: bsl {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
520 ; CHECK: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
530 ; CHECK: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
539 ; CHECK: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
548 ; CHECK: bsl {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
557 ; CHECK: bsl {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
566 ; CHECK: bsl {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
576 ; CHECK: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
586 ; CHECK: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
[all …]
Darm64-vselect.ll13 ;CHECK: bsl.16b v0, v2, v3
Dfp16-vector-shuffle.ll6 ; CHECK: bsl
21 ; CHECK: bsl
/external/libvpx/libvpx/vp9/common/
Dvp9_onyxc_int.h450 const int bsl = mi_width_log2_lookup[bsize]; in partition_plane_context() local
451 int above = (*above_ctx >> bsl) & 1 , left = (*left_ctx >> bsl) & 1; in partition_plane_context()
454 assert(bsl >= 0); in partition_plane_context()
456 return (left * 2 + above) + bsl * PARTITION_PLOFFSET; in partition_plane_context()
Dvp9_mfqe.c225 const int bsl = b_width_log2_lookup[bs]; in mfqe_partition() local
226 PARTITION_TYPE partition = partition_lookup[bsl][cur_bs]; in mfqe_partition()
/external/llvm/test/MC/AArch64/
Dneon-bitwise-instructions.s43 bsl v0.8b, v1.8b, v2.8b
44 bsl v0.16b, v1.16b, v2.16b
Dneon-diagnostics.s74 bsl v0.8b, v1.16b, v2.8b
75 bsl v0.2s, v1.2s, v2.2s
Darm64-advsimd.s545 bsl.8b v0, v0, v0
552 ; CHECK: bsl.8b v0, v0, v0 ; encoding: [0x00,0x1c,0x60,0x2e]
/external/libavc/common/armv8/
Dih264_resi_trans_quant_av8.s226 bsl v4.8b, v20.8b, v24.8b //restore sign of row 1 and 2
227 bsl v5.8b, v21.8b, v25.8b //restore sign of row 3 and 4
228 bsl v6.8b, v22.8b, v26.8b //restore sign of row 1 and 2
229 bsl v7.8b, v23.8b, v27.8b //restore sign of row 3 and 4
449 bsl v4.8b, v20.8b, v24.8b //restore sign of row 1 and 2
450 bsl v5.8b, v21.8b, v25.8b //restore sign of row 3 and 4
451 bsl v6.8b, v22.8b, v26.8b //restore sign of row 1 and 2
452 bsl v7.8b, v23.8b, v27.8b //restore sign of row 3 and 4
599 bsl v4.16b, v14.16b, v15.16b
600 bsl v5.16b, v16.16b, v17.16b
[all …]
/external/libvpx/libvpx/vp9/encoder/
Dvp9_encodeframe.c1428 const int bsl = b_width_log2_lookup[bsize], hbs = (1 << bsl) / 4; in encode_sb() local
1444 partition = partition_lookup[bsl][subsize]; in encode_sb()
1767 const int bsl = b_width_log2_lookup[bsize], hbs = (1 << bsl) / 4; in encode_sb_rt() local
1785 partition = partition_lookup[bsl][subsize]; in encode_sb_rt()
1843 const int bsl = b_width_log2_lookup[bsize]; in rd_use_partition() local
1845 const int bss = (1 << bsl) / 4; in rd_use_partition()
1868 partition = partition_lookup[bsl][bs_type]; in rd_use_partition()
2975 int bsl = b_width_log2_lookup[bsize], hbs = (1 << bsl) / 4; in fill_mode_info_sb() local
3313 const int bsl = b_width_log2_lookup[bsize], hbs = (1 << bsl) / 4; in nonrd_select_partition() local
3324 partition = partition_lookup[bsl][subsize]; in nonrd_select_partition()
[all …]
Dvp9_bitstream.c433 const int bsl = b_width_log2_lookup[bsize]; in write_modes_sb() local
434 const int bs = (1 << bsl) / 4; in write_modes_sb()
444 partition = partition_lookup[bsl][m->mbmi.sb_type]; in write_modes_sb()
Dvp9_rdopt.c2427 int bsl = mi_width_log2_lookup[bsize]; in handle_inter_mode() local
2429 (((mi_row + mi_col) >> bsl) + in handle_inter_mode()
3189 const int bsl = mi_width_log2_lookup[bsize]; in vp9_rd_pick_inter_mode_sb() local
3190 int cb_partition_search_ctrl = (((mi_row + mi_col) >> bsl) in vp9_rd_pick_inter_mode_sb()
Dvp9_pickmode.c1107 const int bsl = mi_width_log2_lookup[bsize]; in vp9_pick_inter_mode() local
1109 (((mi_row + mi_col) >> bsl) + in vp9_pick_inter_mode()
/external/libvpx/libvpx/vp9/decoder/
Dvp9_decodeframe.c907 int bsl) { in dec_partition_plane_context() argument
910 int above = (*above_ctx >> bsl) & 1 , left = (*left_ctx >> bsl) & 1; in dec_partition_plane_context()
914 return (left * 2 + above) + bsl * PARTITION_PLOFFSET; in dec_partition_plane_context()
933 int has_rows, int has_cols, int bsl) { in read_partition() argument
934 const int ctx = dec_partition_plane_context(xd, mi_row, mi_col, bsl); in read_partition()
/external/vixl/src/vixl/a64/
Dsimulator-a64.h1640 LogicVRegister bsl(VectorFormat vform,
Dmacro-assembler-a64.h2119 V(bsl, Bsl) \
Dassembler-a64.h2638 void bsl(const VRegister& vd,
/external/valgrind/none/tests/arm64/
Dfp_and_simd.c2796 GEN_BINARY_TEST(bsl, 16b, 16b, 16b)
2797 GEN_BINARY_TEST(bsl, 8b, 8b, 8b)
/external/vixl/test/
Dtest-simulator-a64.cc3780 DEFINE_TEST_NEON_3SAME_8B_16B(bsl, Basic)
/external/vixl/doc/
Dsupported-instructions.md1529 void bsl(const VRegister& vd,

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