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Searched refs:cycles (Results 1 – 25 of 157) sorted by relevance

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/external/llvm/lib/Target/ARM/
DARMScheduleA9.td82 // No operand cycles
203 // FIXME: If address is 64-bit aligned, AGU cycles is 1.
347 // FIXME: If address is 64-bit aligned, AGU cycles is 1.
469 // Extra latency cycles since wbck is 2 cycles
478 // Extra latency cycles since wbck is 2 cycles
488 // Extra latency cycles since wbck is 4 cycles
497 // Extra latency cycles since wbck is 4 cycles
669 // Extra 1 latency cycle since wbck is 2 cycles
678 // Extra 1 latency cycle since wbck is 2 cycles
719 // FIXME: assumes 2 doubles which requires 2 LS cycles.
[all …]
/external/antlr/antlr-3.4/tool/src/main/java/org/antlr/tool/
DLeftRecursionCyclesMessage.java39 public Collection cycles; field in LeftRecursionCyclesMessage
41 public LeftRecursionCyclesMessage(Collection cycles) { in LeftRecursionCyclesMessage() argument
43 this.cycles = cycles; in LeftRecursionCyclesMessage()
48 st.add("listOfCycles", cycles); in toString()
/external/autotest/client/cros/
Dstorage.py274 storages = self.wait_for_devices(filter_dict, cycles=1,
292 def wait_for_devices(self, storage_filter, time_to_sleep=1, cycles=10, argument
310 '%d secs' % (storage_filter, cycles, time_to_sleep))
316 if cycles == -1:
321 while cycles == -1 or cycle < cycles:
339 (storage_filter, time_to_sleep*cycles))
343 def wait_for_device(self, storage_filter, time_to_sleep=1, cycles=10, argument
368 cycles=cycles,
/external/boringssl/linux-arm/crypto/sha/
Dsha256-armv4.S15 @ lute" terms is ~2250 cycles per 64-byte block or ~35 cycles per
21 @ Cortex A8 core and ~20 cycles per processed byte.
26 @ improvement on Cortex A8 core and ~15.4 cycles per processed byte.
31 @ byte in 12.5 cycles or 23% faster than integer-only code. Snapdragon
32 @ S4 does it in 12.5 cycles too, but it's 50% faster than integer-only
Dsha512-armv4.S15 @ by gcc 3.4 and it spends ~72 clock cycles per byte [on single-issue
21 @ Cortex A8 core and ~40 cycles per processed byte.
26 @ improvement on Coxtex A8 core and ~38 cycles per byte.
31 @ one byte in 23.3 cycles or ~60% faster than integer-only code.
/external/autotest/client/tests/signaltest/src/
Dsignaltest.c54 unsigned long cycles; member
154 if (!par->id && !(stat->cycles & 0x0F)) in signalthread()
185 stat->cycles++; in signalthread()
188 stat->values[stat->cycles & par->bufmsk] = diff; in signalthread()
190 if (par->max_cycles && par->max_cycles == stat->cycles) in signalthread()
300 stat->cycles, stat->min, stat->act, in print_stat()
301 stat->cycles ? in print_stat()
302 (long)(stat->avg/stat->cycles) : 0, stat->max); in print_stat()
305 while (stat->cycles != stat->cyclesread) { in print_stat()
398 if(max_cycles && stat[0].cycles >= max_cycles) in main()
/external/webrtc/webrtc/modules/audio_coding/neteq/tools/
Drtp_analyze.cc106 int cycles = -1; in main() local
132 if (cycles == -1) { in main()
135 cycles = 0; in main()
148 cycles++; in main()
157 64.0 * cycles; in main()
/external/fio/
Dgettime.c261 uint64_t minc, maxc, avg, cycles[NR_TIME_ITERS]; in calibrate_cpu_clock() local
264 cycles[0] = get_cycles_per_usec(); in calibrate_cpu_clock()
267 cycles[i] = get_cycles_per_usec(); in calibrate_cpu_clock()
268 delta = cycles[i] - mean; in calibrate_cpu_clock()
271 S += delta * (cycles[i] - mean); in calibrate_cpu_clock()
279 if (!cycles[0] && !cycles[NR_TIME_ITERS - 1]) in calibrate_cpu_clock()
287 double this = cycles[i]; in calibrate_cpu_clock()
289 minc = min(cycles[i], minc); in calibrate_cpu_clock()
290 maxc = max(cycles[i], maxc); in calibrate_cpu_clock()
303 (unsigned long long) cycles[i] / 10); in calibrate_cpu_clock()
/external/mesa3d/src/gallium/drivers/llvmpipe/
Dlp_test_conv.c66 double cycles, in write_tsv_row() argument
71 fprintf(fp, "%.1f\t", cycles / MAX2(src_type.length, dst_type.length)); in write_tsv_row()
163 int64_t cycles[LP_TEST_NUM_SAMPLES]; in test_one() local
246 cycles[i] = end_counter - start_counter; in test_one()
299 sum += cycles[i]; in test_one()
300 sum2 += cycles[i]*cycles[i]; in test_one()
309 if(fabs(cycles[i] - avg) <= 4.0*std) { in test_one()
310 sum += cycles[i]; in test_one()
Dlp_test_blend.c85 double cycles, in write_tsv_row() argument
91 fprintf(fp, "%.1f\t", cycles / type.length); in write_tsv_row()
96 fprintf(fp, "%.1f\t", cycles / (4 * type.length)); in write_tsv_row()
470 int64_t cycles[LP_TEST_NUM_SAMPLES]; in test_one() local
523 cycles[i] = end_counter - start_counter; in test_one()
603 cycles[i] = end_counter - start_counter; in test_one()
660 sum += cycles[i]; in test_one()
661 sum2 += cycles[i]*cycles[i]; in test_one()
670 if(fabs(cycles[i] - avg) <= 4.0*std) { in test_one()
671 sum += cycles[i]; in test_one()
/external/snakeyaml/src/test/java/org/yaml/snakeyaml/stress/
DParallelTest.java60 int cycles = 200; in run() local
61 for (int i = 0; i < cycles; i++) { in run()
66 float duration = ((time2 - time1) / 1000000) / (float) cycles; in run()
/external/mesa3d/src/mesa/math/
Dm_debug_xform.c169 int mtype, unsigned long *cycles ) in test_transform_function() argument
179 (void) cycles; in test_transform_function()
246 BEGIN_RACE( *cycles ); in test_transform_function()
248 END_RACE( *cycles ); in test_transform_function()
314 unsigned long *cycles = &(benchmark_tab[psize-1][mtype]); in _math_test_all_transform_functions() local
316 if ( test_transform_function( func, psize, mtype, cycles ) == 0 ) { in _math_test_all_transform_functions()
Dm_debug_norm.c196 static int test_norm_function( normal_func func, int mtype, long *cycles ) in test_norm_function() argument
209 (void) cycles; in test_norm_function()
285 BEGIN_RACE( *cycles ); in test_norm_function()
287 END_RACE( *cycles ); in test_norm_function()
359 long *cycles = &benchmark_tab[mtype]; in _math_test_all_normal_transform_functions() local
361 if ( test_norm_function( func, mtype, cycles ) == 0 ) { in _math_test_all_normal_transform_functions()
Dm_debug_clip.c230 int psize, long *cycles ) in test_cliptest_function() argument
241 (void) cycles; in test_cliptest_function()
282 BEGIN_RACE( *cycles ); in test_cliptest_function()
284 END_RACE( *cycles ); in test_cliptest_function()
384 long *cycles = &(benchmark_tab[np][psize-1]); in _math_test_all_cliptest_functions() local
386 if ( test_cliptest_function( func, np, psize, cycles ) == 0 ) { in _math_test_all_cliptest_functions()
/external/autotest/server/tests/netperf2/
Dnetperf2.py7 def run_once(self, pair, test, time, stream_list, cycles): argument
44 time, stream_list, 'server', cycles)
46 time, stream_list, 'client', cycles)
/external/autotest/client/tests/cyclictest/src/
Dcyclictest.c73 unsigned long cycles; member
331 stat->cycles++; in timerthread()
334 stat->values[stat->cycles & par->bufmsk] = diff; in timerthread()
340 if (par->max_cycles && par->max_cycles == stat->cycles) in timerthread()
506 stat->cycles, stat->min, stat->act, in print_stat()
507 stat->cycles ? in print_stat()
508 (long)(stat->avg/stat->cycles) : 0, stat->max); in print_stat()
511 while (stat->cycles != stat->cyclesread) { in print_stat()
597 if(max_cycles && stat[i].cycles >= max_cycles) in main()
/external/netperf/
DREADME.hpux13 HOWEVER... there is a bug in the accounting for interrupt cycles,
14 where interrupt cycles go missing. SOOO, since there is an accurate
15 way to know what the total number of cycles should have been over the
18 ratio of idle to total cycles to compute CPU util.
/external/autotest/server/tests/netpipe/
Dcontrol.stress.srv11 If you need to adjust the run time, change the value of cycles in the run
28 cycles - Number of times to repeat each test. Each cycle takes about 6
41 cycles = 10
46 for x in xrange(cycles):
/external/autotest/client/site_tests/power_LoadTest/extension/
Dtest.js6 var cycles = {}; variable
94 cycles[task.name] = cycle;
108 for (var name in cycles) {
109 var cycle = cycles[name];
/external/autotest/client/profilers/cpistat/
Dcpistat77 cycles = sum['PERF_COUNT_HW_CPU_CYCLES'] variable
79 CPI = cycles * 1.0/instructions
81 % (cycles, instructions, CPI))
/external/autotest/client/site_tests/hardware_PerfCounterVerification/
Dcontrol34 perf_cmd='stat', events=('cycles', 'instructions'),
42 perf_cmd='stat', events=('iTLB-misses','cycles'),
46 perf_cmd='stat', events=('dTLB-misses','cycles'),
/external/ceres-solver/data/nist/
DENSO.dat15 reveals 3 significant cycles. The annual cycle is the
16 strongest, but cycles with periods of approximately 44
17 and 26 months are also present. These cycles
/external/autotest/client/site_tests/power_CPUIdle/
Dcontrol8 CRITERIA = "Fails if the cpu did not have any idle cycles during this test."
18 determine idle cycles.
/external/autotest/client/site_tests/network_3GStressEnable/
Dnetwork_3GStressEnable.py46 def run_once(self, test_env, cycles=3, min=15, max=25): argument
51 for n in xrange(cycles):
/external/autotest/client/tests/tsc/src/
DREADME5 The test passes if all TSCs are within +/- "threshold" clock cycles
6 of each other. The default value of "threshold" is 500 clock cycles

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