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Searched refs:dclz (Results 1 – 25 of 28) sorted by relevance

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/external/llvm/test/CodeGen/Mips/
Dmips64instrs.ll189 ; The MIPS4 version is too long to reasonably test. At least check we don't get dclz
190 ; MIPS4-NOT: dclz
192 ; HAS-DCLO: dclz $2, $4
Dcountleading.ll49 ; MIPS4-NOT: dclz
60 ; MIPS64-GT-R1: dclz $2, $4
/external/llvm/test/MC/Mips/mips32/
Dinvalid-mips64.s9 …dclz $s0,$t9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not curr…
/external/valgrind/none/tests/mips64/
Darithmetic_instruction.stdout.exp-mips64r28449 dclz $t0, $t1 :: rd 0x40, rs 0x0
8450 dclz $v0, $v1 :: rd 0x27, rs 0x12bd6aa
8451 dclz $t0, $t1 :: rd 0x40, rs 0x0
8452 dclz $v0, $v1 :: rd 0x9, rs 0x7e876382d2ab13
8453 dclz $t0, $t1 :: rd 0x24, rs 0x9823b6e
8454 dclz $v0, $v1 :: rd 0x0, rs 0x976d6e9ac31510f3
8455 dclz $t0, $t1 :: rd 0x24, rs 0xd4326d9
8456 dclz $v0, $v1 :: rd 0x0, rs 0xb7746d775ad6a5fb
8457 dclz $t0, $t1 :: rd 0x23, rs 0x130476dc
8458 dclz $v0, $v1 :: rd 0x1, rs 0x42b0c0a28677b502
[all …]
Darithmetic_instruction.stdout.exp-mips648449 dclz $t0, $t1 :: rd 0x40, rs 0x0
8450 dclz $v0, $v1 :: rd 0x27, rs 0x12bd6aa
8451 dclz $t0, $t1 :: rd 0x40, rs 0x0
8452 dclz $v0, $v1 :: rd 0x9, rs 0x7e876382d2ab13
8453 dclz $t0, $t1 :: rd 0x24, rs 0x9823b6e
8454 dclz $v0, $v1 :: rd 0x0, rs 0x976d6e9ac31510f3
8455 dclz $t0, $t1 :: rd 0x24, rs 0xd4326d9
8456 dclz $v0, $v1 :: rd 0x0, rs 0xb7746d775ad6a5fb
8457 dclz $t0, $t1 :: rd 0x23, rs 0x130476dc
8458 dclz $v0, $v1 :: rd 0x1, rs 0x42b0c0a28677b502
[all …]
/external/llvm/test/MC/Mips/mips4/
Dinvalid-mips64.s12 …dclz $s0,$t9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature no…
Dinvalid-mips64r2.s11 …dclz $s0,$t9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
/external/llvm/test/MC/Mips/mips5/
Dinvalid-mips64.s11 …dclz $s0,$25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature no…
Dinvalid-mips64r2.s11 …dclz $s0,$25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
/external/llvm/lib/Target/Mips/
DMips64r6InstrInfo.td15 // Reencoded: dclo, dclz
62 class DCLZ_R6_DESC : CLZ_R6_DESC_BASE<"dclz", GPR64Opnd>;
DMips64InstrInfo.td263 def DCLZ : CountLeading0<"dclz", GPR64Opnd>, CLO_FM<0x24>, ISA_MIPS64_NOT_64R6;
/external/llvm/test/MC/Mips/mips64/
Dvalid.s77 dclz $s0,$25 # CHECK: dclz $16, $25 # encoding: [0x73,0x30,0x80,0x24]
/external/llvm/test/MC/Mips/mips64r2/
Dvalid.s77 dclz $s0,$25 # CHECK: dclz $16, $25 # encoding: [0x73,0x30,0x80,0x24]
/external/llvm/test/MC/Mips/mips64r5/
Dvalid.s77 dclz $s0,$25 # CHECK: dclz $16, $25 # encoding: [0x73,0x30,0x80,0x24]
/external/llvm/test/MC/Mips/mips64r3/
Dvalid.s77 dclz $s0,$25 # CHECK: dclz $16, $25 # encoding: [0x73,0x30,0x80,0x24]
/external/llvm/test/MC/Disassembler/Mips/mips64r2/
Dvalid-mips64r2-el.txt88 0x24 0x80 0x30 0x73 # CHECK: dclz $16, $25
267 0x24 0xd0 0x3a 0x71 # CHECK: dclz $26, $9
Dvalid-mips64r2.txt407 0x71 0x3a 0xd0 0x24 # CHECK: dclz $26, $9
409 0x73 0x30 0x80 0x24 # CHECK: dclz $16, $25
/external/llvm/test/MC/Disassembler/Mips/mips64r6/
Dvalid-mips64r6-el.txt87 0x52 0x80 0x20 0x03 # CHECK: dclz $16, $25
Dvalid-mips64r6.txt46 0x03 0x20 0x80 0x52 # CHECK: dclz $16, $25
/external/llvm/test/MC/Disassembler/Mips/mips64r5/
Dvalid-mips64r5.txt405 0x71 0x3a 0xd0 0x24 # CHECK: dclz $26, $9
407 0x73 0x30 0x80 0x24 # CHECK: dclz $16, $25
Dvalid-mips64r5-el.txt85 0x24 0x80 0x30 0x73 # CHECK: dclz $16, $25
/external/llvm/test/MC/Disassembler/Mips/mips64r3/
Dvalid-mips64r3.txt405 0x71 0x3a 0xd0 0x24 # CHECK: dclz $26, $9
407 0x73 0x30 0x80 0x24 # CHECK: dclz $16, $25
Dvalid-mips64r3-el.txt85 0x24 0x80 0x30 0x73 # CHECK: dclz $16, $25
/external/llvm/test/MC/Disassembler/Mips/mips64/
Dvalid-mips64-el.txt82 0x24 0x80 0x30 0x73 # CHECK: dclz $16, $25
Dvalid-mips64.txt381 0x73 0x30 0x80 0x24 # CHECK: dclz $16, $25

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