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Searched refs:dmb (Results 1 – 25 of 58) sorted by relevance

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/external/llvm/test/CodeGen/ARM/
Doptimize-dmbs-v7.ll23 ; Hence it should have 3 dmb;str;dmb sequences with the middle dmbs collapsed
26 ; CHECK: dmb
27 ; CHECK-NOT: dmb
31 ; CHECK: dmb
32 ; CHECK-NOT: dmb
36 ; CHECK: dmb
37 ; CHECK-NOT: dmb
41 ; CHECK: dmb
42 ; CHECK-NOT: dmb
48 call void @llvm.arm.dmb(i32 11)
[all …]
Datomic-load-store.ll11 ; ARM: dmb {{ish$}}
13 ; ARM-NEXT: dmb {{ish$}}
17 ; THUMBTWO: dmb {{ish$}}
19 ; THUMBTWO-NEXT: dmb {{ish$}}
25 ; THUMBM: dmb sy
27 ; THUMBM: dmb sy
35 ; ARM-NEXT: dmb {{ish$}}
40 ; THUMBTWO-NEXT: dmb {{ish$}}
46 ; THUMBM: dmb sy
53 ; ARM-NOT: dmb
[all …]
Dswift-atomics.ll4 ; Release operations only need the store barrier provided by a "dmb ishst",
8 ; CHECK: dmb ishst
12 ; CHECK-STRICT-ATOMIC: dmb {{ish$}}
18 ; followed by an acquire does not get reordered. In that case a "dmb ishst" is
22 ; CHECK: dmb ishst
24 ; CHECK: dmb {{ish$}}
26 ; CHECK: dmb {{ish$}}
29 ; CHECK-STRICT-ATOMIC: dmb {{ish$}}
31 ; CHECK-STRICT-ATOMIC: dmb {{ish$}}
33 ; CHECK-STRICT-ATOMIC: dmb {{ish$}}
[all …]
Datomic-64bit.ll8 ; CHECK: dmb {{ish$}}
17 ; CHECK: dmb {{ish$}}
20 ; CHECK-THUMB: dmb {{ish$}}
29 ; CHECK-THUMB: dmb {{ish$}}
37 ; CHECK: dmb {{ish$}}
46 ; CHECK: dmb {{ish$}}
49 ; CHECK-THUMB: dmb {{ish$}}
58 ; CHECK-THUMB: dmb {{ish$}}
66 ; CHECK: dmb {{ish$}}
75 ; CHECK: dmb {{ish$}}
[all …]
Datomic-ops-v8.ll14 ; CHECK-NOT: dmb
27 ; CHECK-NOT: dmb
37 ; CHECK-NOT: dmb
50 ; CHECK-NOT: dmb
60 ; CHECK-NOT: dmb
73 ; CHECK-NOT: dmb
83 ; CHECK-NOT: dmb
99 ; CHECK-NOT: dmb
110 ; CHECK-NOT: dmb
123 ; CHECK-NOT: dmb
[all …]
Dintrinsics-v8.ll4 ; CHECK: dmb sy
5 call void @llvm.arm.dmb(i32 15)
6 ; CHECK: dmb osh
7 call void @llvm.arm.dmb(i32 3)
17 declare void @llvm.arm.dmb(i32)
Dcmpxchg-idioms.ll6 ; CHECK: dmb ishst
18 ; CHECK: dmb ish
24 ; CHECK: dmb ish
37 ; CHECK: dmb ishst
70 ; CHECK: dmb ishst
82 ; CHECK: dmb ish
87 ; CHECK: dmb ish
Dprint-memb-operand.ll3 ; CHECK: dmb ld
6 call void @llvm.arm.dmb(i32 13)
10 declare void @llvm.arm.dmb(i32)
Dintrinsics-memory-barrier.ll6 call void @llvm.arm.dmb(i32 3) ; CHECK: dmb osh
19 call void @llvm.arm.dmb(i32 15) ; CHECK: dmb sy
53 declare void @llvm.arm.dmb(i32)
Dnoopt-dmb-v7.ll13 ; CHECK-NEXT: dmb ish
14 ; CHECK-NEXT: dmb ish
15 ; CHECK-NEXT: dmb ish
Datomic-op.ll275 ; CHECK-ARMV7: dmb ish
283 ; CHECK-ARMV7: dmb ish
289 ; CHECK-T2: dmb ish
309 ; CHECK-NOT: dmb ish
321 ; CHECK: dmb ish
334 ; CHECK: dmb
336 ; CHECK: dmb
343 ; CHECK-BAREMETAL-NOT: dmb
345 ; CHECK-BAREMETAL-NOT: dmb
356 ; CHECK: dmb
[all …]
Dcmpxchg-weak.ll9 ; CHECK-NEXT: dmb ish
18 ; CHECK-NEXT: dmb ish
39 ; CHECK-NEXT: dmb ish
48 ; CHECK-NEXT: dmb ish
/external/llvm/test/CodeGen/AArch64/
Datomic-ops.ll18 ; CHECK-NOT: dmb
29 ; CHECK-NOT: dmb
38 ; CHECK-NOT: dmb
49 ; CHECK-NOT: dmb
58 ; CHECK-NOT: dmb
69 ; CHECK-NOT: dmb
78 ; CHECK-NOT: dmb
89 ; CHECK-NOT: dmb
98 ; CHECK-NOT: dmb
109 ; CHECK-NOT: dmb
[all …]
Dintrinsics-memory-barrier.ll4 ; CHECK: dmb sy
5 call void @llvm.aarch64.dmb(i32 15)
6 ; CHECK: dmb osh
7 call void @llvm.aarch64.dmb(i32 3)
23 call void @llvm.aarch64.dmb(i32 15); CHECK: dmb sy
55 declare void @llvm.aarch64.dmb(i32)
Darm64-atomic-128.ll169 ; CHECK-NOT: dmb
171 ; CHECK-NOT: dmb
178 ; CHECK-NOT: dmb
183 ; CHECK-NOT: dmb
191 ; CHECK-NOT: dmb
196 ; CHECK-NOT: dmb
203 ; CHECK-NOT: dmb
208 ; CHECK-NOT: dmb
215 ; CHECK-NOT: dmb
220 ; CHECK-NOT: dmb
Datomic-ops-not-barriers.ll16 ; CHECK: dmb
18 ; CHECK: dmb
19 ; The key point here is that the second dmb isn't immediately followed by the
/external/llvm/test/MC/ARM/
Dbasic-arm-instructions-v8.s22 dmb ishld
23 dmb oshld
24 dmb nshld
25 dmb ld
27 @ CHECK-V8: dmb ishld @ encoding: [0x59,0xf0,0x7f,0xf5]
28 @ CHECK-V8: dmb oshld @ encoding: [0x51,0xf0,0x7f,0xf5]
29 @ CHECK-V8: dmb nshld @ encoding: [0x55,0xf0,0x7f,0xf5]
30 @ CHECK-V8: dmb ld @ encoding: [0x5d,0xf0,0x7f,0xf5]
Dbasic-thumb2-instructions-v8.s52 dmb ishld
53 dmb oshld
54 dmb nshld
55 dmb ld
57 @ CHECK-V8: dmb ishld @ encoding: [0xbf,0xf3,0x59,0x8f]
58 @ CHECK-V8: dmb oshld @ encoding: [0xbf,0xf3,0x51,0x8f]
59 @ CHECK-V8: dmb nshld @ encoding: [0xbf,0xf3,0x55,0x8f]
60 @ CHECK-V8: dmb ld @ encoding: [0xbf,0xf3,0x5d,0x8f]
Dthumb-hints.s22 dmb sy
23 dmb
28 @ CHECK: dmb sy @ encoding: [0xbf,0xf3,0x5f,0x8f]
29 @ CHECK: dmb sy @ encoding: [0xbf,0xf3,0x5f,0x8f]
49 @ CHECK-ERROR-NEXT: dmb sy
52 @ CHECK-ERROR-NEXT: dmb
Dinvalid-barrier.s7 dmb #0x10
8 dmb imaginary_scope
/external/llvm/test/Transforms/AtomicExpand/ARM/
Datomic-expansion-v7.ll5 ; CHECK-NOT: dmb
15 ; CHECK-NOT: dmb
23 ; CHECK: call void @llvm.arm.dmb(i32 11)
34 ; CHECK: call void @llvm.arm.dmb(i32 11)
42 ; CHECK-NOT: dmb
51 ; CHECK: call void @llvm.arm.dmb(i32 11)
59 ; CHECK: call void @llvm.arm.dmb(i32 11)
70 ; CHECK-NOT: dmb
78 ; CHECK: call void @llvm.arm.dmb(i32 11)
90 ; CHECK: call void @llvm.arm.dmb(i32 11)
[all …]
Dcmpxchg-weak.ll5 ; Intrinsic for "dmb ishst" is then expected
6 ; CHECK: call void @llvm.arm.dmb(i32 10)
20 ; CHECK: call void @llvm.arm.dmb(i32 11)
28 ; CHECK: call void @llvm.arm.dmb(i32 11)
42 ; CHECK: call void @llvm.arm.dmb(i32 10)
56 ; CHECK: call void @llvm.arm.dmb(i32 11)
64 ; CHECK-NOT: dmb
78 ; CHECK-NOT: dmb
92 ; CHECK-NOT: dmb
100 ; CHECK-NOT: dmb
/external/llvm/test/MC/Disassembler/ARM/
Dthumb-v8.txt26 # CHECK: dmb ishld
27 # CHECK: dmb oshld
28 # CHECK: dmb nshld
29 # CHECK: dmb ld
Dbasic-arm-instructions-v8.txt17 # CHECK: dmb ishld
18 # CHECK: dmb oshld
19 # CHECK: dmb nshld
20 # CHECK: dmb ld
/external/compiler-rt/lib/builtins/arm/
Dsync-ops.h23 dmb ; \
31 dmb ; \
40 dmb ; \
48 dmb ; \

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