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Searched refs:ds_read_b32 (Results 1 – 16 of 16) sorted by relevance

/external/llvm/test/CodeGen/AMDGPU/
Dds-negative-offset-addressing-mode-loop.ll12 ; SI-DAG: ds_read_b32 v{{[0-9]+}}, [[VADDR]]
14 ; SI-DAG: ds_read_b32 v{{[0-9]+}}, [[VADDR4]]
16 ; SI-DAG: ds_read_b32 v{{[0-9]+}}, [[VADDR0x80]]
18 ; SI-DAG: ds_read_b32 v{{[0-9]+}}, [[VADDR0x84]]
20 ; SI-DAG: ds_read_b32 v{{[0-9]+}}, [[VADDR0x100]]
24 ; CI-DAG: ds_read_b32 v{{[0-9]+}}, [[VADDR]] offset:256
Dsi-triv-disjoint-mem-access.ll13 ; CI: ds_read_b32 {{v[0-9]+}}, {{v[0-9]+}} offset:4
14 ; CI-NEXT: ds_read_b32 {{v[0-9]+}}, {{v[0-9]+}} offset:8
33 ; CI: ds_read_b32 {{v[0-9]+}}, {{v[0-9]+}} offset:4
35 ; CI: ds_read_b32 {{v[0-9]+}}, {{v[0-9]+}} offset:8
53 ; CI: ds_read_b32 {{v[0-9]+}}, {{v[0-9]+}} offset:4
54 ; CI: ds_read_b32 {{v[0-9]+}}, {{v[0-9]+}} offset:8
158 ; CI: ds_read_b32 {{v[0-9]+}}, {{v[0-9]+}} offset:400
159 ; CI: ds_read_b32 {{v[0-9]+}}, {{v[0-9]+}} offset:404
211 ; XCI: ds_read_b32 {{v[0-9]+}}, {{v[0-9]+}}, 0x4
213 ; XCI: ds_read_b32 {{v[0-9]+}}, {{v[0-9]+}}, 0x8
D32-bit-local-address-space.ll15 ; SI: ds_read_b32 v{{[0-9]+}}, [[PTR]]
26 ; SI: ds_read_b32 [[VPTR]]
37 ; SI: ds_read_b32 v{{[0-9]+}}, [[VPTR]] offset:4
50 ; SI: ds_read_b32 [[VPTR]]
73 ; SI: ds_read_b32
85 ; SI: ds_read_b32 v{{[0-9]+}}, [[REG]]
Daddress-space.ll11 ; CHECK-DAG: ds_read_b32 v{{[0-9]+}}, [[VREG1]] offset:12
12 ; CHECK-DAG: ds_read_b32 v{{[0-9]+}}, [[VREG1]] offset:20
Dlocal-memory-two-objects.ll34 ; SI: ds_read_b32 {{v[0-9]+}}, [[SIPTR]]
35 ; CI: ds_read_b32 {{v[0-9]+}}, [[ADDRR:v[0-9]+]] offset:16
36 ; CI: ds_read_b32 {{v[0-9]+}}, [[ADDRR]]
Dds_read2.ll49 ; SI: ds_read_b32 v{{[0-9]+}}, v{{[0-9]+}}
50 ; SI: ds_read_b32 v{{[0-9]+}}, v{{[0-9]+}} offset:1028
170 ; SI: ds_read_b32
171 ; SI: ds_read_b32
196 ; SI: ds_read_b32
197 ; SI: ds_read_b32
243 ; SI: ds_read_b32 v{{[0-9]+}}, v{{[0-9]+}}
244 ; SI: ds_read_b32 v{{[0-9]+}}, v{{[0-9]+}} offset:32
261 ; SI: ds_read_b32 v{{[0-9]+}}, v{{[0-9]+}}
262 ; SI: ds_read_b32 v{{[0-9]+}}, v{{[0-9]+}} offset:32
Dlocal-memory.ll28 ; SI: ds_read_b32 {{v[0-9]+}},
Dds_read2_offset_order.ll14 ; SI: ds_read_b32 v{{[0-9]+}}, v{{[0-9]+}} offset:44
Dlocal-64.ll6 ; BOTH: ds_read_b32 [[REG:v[0-9]+]], v{{[0-9]+}} offset:28
16 ; BOTH: ds_read_b32 [[REG:v[0-9]+]], v{{[0-9]+}}
Dload.ll624 ; SI: ds_read_b32
636 ; SI: ds_read_b32
662 ; SI-DAG: ds_read_b32
682 ; SI: ds_read_b32 v0, v[[ZERO]] offset:4
Dshl_add_ptr.ll20 ; SI: ds_read_b32 {{v[0-9]+}}, [[PTR]] offset:8
37 ; SI: ds_read_b32 [[RESULT:v[0-9]+]], [[PTR]] offset:8
Dds_read2st64.ll69 ; SI: ds_read_b32 {{v[0-9]+}}, {{v[0-9]+}} offset:256
70 ; SI: ds_read_b32 {{v[0-9]+}}, [[BIGADD]]
Dprivate-memory.ll24 ; SI-PROMOTE: ds_read_b32
25 ; SI-PROMOTE: ds_read_b32
Dds_read2_superreg.ll66 ; CI-DAG: ds_read_b32 v[[REG_Z:[0-9]+]], v{{[0-9]+}} offset:8{{$}}
/external/llvm/test/MC/AMDGPU/
Dds.s180 ds_read_b32 v8, v2 label
/external/llvm/lib/Target/AMDGPU/
DSIInstructions.td820 defm DS_READ_B32 : DS_1A_RET <0x36, "ds_read_b32", VGPR_32>;