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Searched refs:dsub (Results 1 – 25 of 46) sorted by relevance

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/external/valgrind/none/tests/ppc64/
Dtest_dfp1.stdout.exp55 dsub 2234000000000e50 - 223400000014c000 => a234000000149ad0
56 dsub a2340000000000e0 - 223400000014c000 => a23400000014c0e0
57 dsub 22240000000000cf - a21400010a395bcf => 221400010a571bcf
58 dsub 2234000000000e50 - 000400000089b000 => 2e06500000000000
59 dsub a2340000000000e0 - a21400010a395bcf => a214000477cb0d11
60 dsub 6e4d3f1f534acdd4 - 223400000014c000 => 6e4d3f1f534acdd3
61 dsub 6e4d3f1f534acdd4 - a2340000000000e0 => 6e4d3f1f534acdd4
62 dsub 2238000000000000 - 223400000014c000 => a23400000014c000
63 dsub 2238000000000000 - a2340000000000e0 => 22340000000000e0
64 dsub a238000000000000 - 2234000000000e50 => a234000000000e50
[all …]
/external/valgrind/none/tests/ppc32/
Dtest_dfp1.stdout.exp55 dsub 2234000000000e50 - 223400000014c000 => a234000000149ad0
56 dsub a2340000000000e0 - 223400000014c000 => a23400000014c0e0
57 dsub 22240000000000cf - a21400010a395bcf => 221400010a571bcf
58 dsub 2234000000000e50 - 000400000089b000 => 2e06500000000000
59 dsub a2340000000000e0 - a21400010a395bcf => a214000477cb0d11
60 dsub 6e4d3f1f534acdd4 - 223400000014c000 => 6e4d3f1f534acdd3
61 dsub 6e4d3f1f534acdd4 - a2340000000000e0 => 6e4d3f1f534acdd4
62 dsub 2238000000000000 - 223400000014c000 => a23400000014c000
63 dsub 2238000000000000 - a2340000000000e0 => 22340000000000e0
64 dsub a238000000000000 - 2234000000000e50 => a234000000000e50
[all …]
/external/llvm/test/MC/Mips/
Dmips64-alu-instructions.s84 # CHECK: dsub $9, $6, $7 # encoding: [0x2e,0x48,0xc7,0x00]
109 dsub $9,$6,$7
124 # CHECK: dsub $9, $9, $3 # encoding: [0x2e,0x48,0x23,0x01]
135 dsub $9, $3
137 dsub $9, 10
/external/llvm/lib/Target/AArch64/
DAArch64AdvSIMDScalarPass.cpp127 SubReg == AArch64::dsub); in isFPR64()
130 (AArch64::FPR128RegClass.contains(Reg) && SubReg == AArch64::dsub); in isFPR64()
146 SubReg = AArch64::dsub; in getSrcFromCopy()
DAArch64InstrInfo.td1338 defm : ScalToVecROLoadPat<ro64, load, i64, v2i64, LDRDroW, LDRDroX, dsub>;
1340 defm : ScalToVecROLoadPat<ro64, load, f64, v2f64, LDRDroW, LDRDroX, dsub>;
1503 (LDRDui GPR64sp:$Rn, uimm12s8:$offset), dsub)>;
2039 defm : VecROStoreLane0Pat<ro64, store , v2i64, i64, dsub, STRDroW, STRDroX>;
2040 defm : VecROStoreLane0Pat<ro64, store , v2f64, f64, dsub, STRDroW, STRDroX>;
2734 (FCVTNv8i16 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
2738 (FCVTNv4i32 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
3530 (ADDHNv8i16_v16i8 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3535 (ADDHNv4i32_v8i16 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3540 (ADDHNv2i64_v4i32 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
[all …]
DAArch64RegisterInfo.td28 def dsub : SubRegIndex<32>;
354 let SubRegIndices = [dsub], RegAltNameIndices = [vreg, vlist1] in {
/external/compiler-rt/lib/builtins/
Dsubdf3.c18 ARM_EABI_FNALIAS(dsub, subdf3) in ARM_EABI_FNALIAS() argument
/external/llvm/test/MC/Mips/mips64r2/
Dvalid.s121 dsub $a3,$s6,$8
122 dsub $a3,$s6,$8
123 … dsub $sp,$s4,-27705 # CHECK: daddi $sp, $20, 27705 # encoding: [0x62,0x9d,0x6c,0x39]
124 … dsub $sp,-27705 # CHECK: daddi $sp, $sp, 27705 # encoding: [0x63,0xbd,0x6c,0x39]
/external/llvm/test/MC/Mips/mips64r5/
Dvalid.s121 dsub $a3,$s6,$8
122 dsub $a3,$s6,$8
123 … dsub $sp,$s4,-27705 # CHECK: daddi $sp, $20, 27705 # encoding: [0x62,0x9d,0x6c,0x39]
124 … dsub $sp,-27705 # CHECK: daddi $sp, $sp, 27705 # encoding: [0x63,0xbd,0x6c,0x39]
/external/llvm/test/MC/Mips/mips64r3/
Dvalid.s121 dsub $a3,$s6,$8
122 dsub $a3,$s6,$8
123 … dsub $sp,$s4,-27705 # CHECK: daddi $sp, $20, 27705 # encoding: [0x62,0x9d,0x6c,0x39]
124 … dsub $sp,-27705 # CHECK: daddi $sp, $sp, 27705 # encoding: [0x63,0xbd,0x6c,0x39]
/external/llvm/test/MC/Mips/mips3/
Dvalid.s101 dsub $a3,$s6,$8
102 … dsub $sp,$s4,-27705 # CHECK: daddi $sp, $20, 27705 # encoding: [0x62,0x9d,0x6c,0x39]
103 … dsub $sp,-27705 # CHECK: daddi $sp, $sp, 27705 # encoding: [0x63,0xbd,0x6c,0x39]
/external/llvm/test/MC/Mips/mips64r6/
Dinvalid-mips64.s20 …dsub $sp,$s4,-27705 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
21 …dsub $sp,-27705 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
/external/llvm/test/MC/Mips/mips5/
Dvalid.s105 dsub $a3,$s6,$8
106 … dsub $sp,$s4,-27705 # CHECK: daddi $sp, $20, 27705 # encoding: [0x62,0x9d,0x6c,0x39]
107 … dsub $sp,-27705 # CHECK: daddi $sp, $sp, 27705 # encoding: [0x63,0xbd,0x6c,0x39]
/external/llvm/test/MC/Mips/mips64/
Dvalid.s112 dsub $a3,$s6,$8
113 … dsub $sp,$s4,-27705 # CHECK: daddi $sp, $20, 27705 # encoding: [0x62,0x9d,0x6c,0x39]
114 … dsub $sp,-27705 # CHECK: daddi $sp, $sp, 27705 # encoding: [0x63,0xbd,0x6c,0x39]
/external/llvm/test/MC/Mips/mips4/
Dvalid.s105 dsub $a3,$s6,$8
106 … dsub $sp,$s4,-27705 # CHECK: daddi $sp, $20, 27705 # encoding: [0x62,0x9d,0x6c,0x39]
107 … dsub $sp,-27705 # CHECK: daddi $sp, $sp, 27705 # encoding: [0x63,0xbd,0x6c,0x39]
/external/valgrind/none/tests/mips64/
Darithmetic_instruction.stdout.exp-mips64r211497 dsub $t0, $t1, $t2 :: rd 0x4e08bf4c, rs 0x0, rt 0xffffffffb1f740b4
11498 dsub $t0, $t1, $t2 :: rd 0x4ac9a2fd, rs 0x0, rt 0xffffffffb5365d03
11499 dsub $t0, $t1, $t2 :: rd 0x510cbf94, rs 0x9823b6e, rt 0xffffffffb8757bda
11500 dsub $t0, $t1, $t2 :: rd 0x508ec06c, rs 0xd4326d9, rt 0xffffffffbcb4666d
11501 dsub $t0, $t1, $t2 :: rd 0x70114074, rs 0x130476dc, rt 0xffffffffa2f33668
11502 dsub $t0, $t1, $t2 :: rd 0x71933f8c, rs 0x17c56b6b, rt 0xffffffffa6322bdf
11503 dsub $t0, $t1, $t2 :: rd 0x6f1540ac, rs 0x1a864db2, rt 0xffffffffab710d06
11504 dsub $t0, $t1, $t2 :: rd 0x6e973f54, rs 0x1e475005, rt 0xffffffffafb010b1
11505 dsub $t0, $t1, $t2 :: rd 0x8e0940ac, rs 0x2608edb8, rt 0xffffffff97ffad0c
11506 dsub $t0, $t1, $t2 :: rd 0x8f8b3f54, rs 0x22c9f00f, rt 0xffffffff933eb0bb
[all …]
Darithmetic_instruction.stdout.exp-mips6411497 dsub $t0, $t1, $t2 :: rd 0x4e08bf4c, rs 0x0, rt 0xffffffffb1f740b4
11498 dsub $t0, $t1, $t2 :: rd 0x4ac9a2fd, rs 0x0, rt 0xffffffffb5365d03
11499 dsub $t0, $t1, $t2 :: rd 0x510cbf94, rs 0x9823b6e, rt 0xffffffffb8757bda
11500 dsub $t0, $t1, $t2 :: rd 0x508ec06c, rs 0xd4326d9, rt 0xffffffffbcb4666d
11501 dsub $t0, $t1, $t2 :: rd 0x70114074, rs 0x130476dc, rt 0xffffffffa2f33668
11502 dsub $t0, $t1, $t2 :: rd 0x71933f8c, rs 0x17c56b6b, rt 0xffffffffa6322bdf
11503 dsub $t0, $t1, $t2 :: rd 0x6f1540ac, rs 0x1a864db2, rt 0xffffffffab710d06
11504 dsub $t0, $t1, $t2 :: rd 0x6e973f54, rs 0x1e475005, rt 0xffffffffafb010b1
11505 dsub $t0, $t1, $t2 :: rd 0x8e0940ac, rs 0x2608edb8, rt 0xffffffff97ffad0c
11506 dsub $t0, $t1, $t2 :: rd 0x8f8b3f54, rs 0x22c9f00f, rt 0xffffffff933eb0bb
[all …]
/external/llvm/test/MC/Mips/mips2/
Dinvalid-mips3.s46 …dsub $a3,$s6,$a4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fea…
Dinvalid-mips4.s44 …dsub $a3,$s6,$8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
/external/llvm/test/CodeGen/AArch64/
Darm64-AdvSIMD-Scalar.ll72 ; sub MI doesn't access dsub register.
/external/llvm/lib/Target/Mips/
DMips64InstrInfo.td126 def DSUB : ArithLogicR<"dsub", GPR64Opnd, 0, II_DSUB>, ADD_FM<0, 0x2e>,
610 def : MipsInstAlias<"dsub $rs, $rt, $imm",
614 def : MipsInstAlias<"dsub $rs, $imm",
/external/llvm/test/MC/Mips/mips1/
Dinvalid-mips3.s9 …dsub $a3,$s6,$8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
Dinvalid-mips4.s46 …dsub $a3,$s6,$8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
/external/llvm/test/MC/Disassembler/Mips/mips3/
Dvalid-mips3-el.txt91 0x2e 0x38 0xc8 0x02 # CHECK: dsub $7, $22, $8
Dvalid-mips3.txt86 0x02 0xc8 0x38 0x2e # CHECK: dsub $7, $22, $8

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