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/external/llvm/test/CodeGen/Mips/llvm-ir/
Dselect.ll173 ; M3: mov.s $f13, $f14
177 ; M3: mov.s $f0, $f13
190 ; CMOV-64: movn.s $f14, $f13, $[[T0]]
194 ; SEL-64: sel.s $f0, $f14, $f13
208 ; M3: mov.s $f12, $f13
221 ; CMOV-64: movn.s $f13, $f12, $[[T0]]
222 ; CMOV-64: mov.s $f0, $f13
225 ; SEL-64: sel.s $f0, $f13, $f12
261 ; M3: mov.d $f13, $f14
264 ; M3: mov.d $f0, $f13
[all …]
/external/llvm/test/CodeGen/Mips/
Dfcmp.ll33 ; 64-C-DAG: c.eq.s $f12, $f13
40 ; 64-CMP-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f13
57 ; 64-C-DAG: c.ule.s $f12, $f13
64 ; 64-CMP-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f13, $f12
81 ; 64-C-DAG: c.ult.s $f12, $f13
88 ; 64-CMP-DAG: cmp.le.s $[[T0:f[0-9]+]], $f13, $f12
105 ; 64-C-DAG: c.olt.s $f12, $f13
112 ; 64-CMP-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f12, $f13
129 ; 64-C-DAG: c.ole.s $f12, $f13
136 ; 64-CMP-DAG: cmp.le.s $[[T0:f[0-9]+]], $f12, $f13
[all …]
Dno-odd-spreg-msa.ll14 %b = call float asm sideeffect "mov.s $0, $1", "={$f13},{$f12}" (float %a)
17 ; Clobber all except $f12/$w12 and $f13
20 ; allocator will choose $f12/$w12 for the vector and $f13 for the float to
24 ; must copy $f13 to an even-numbered register before inserting into the
33 ; ALL: mov.s $f13, $f12
36 ; NOODDSPREG: mov.s $f[[F0:[0-9]+]], $f13
48 %b = call float asm sideeffect "mov.s $0, $1", "={$f13},{$f12}" (float %a)
51 ; Clobber all except $f12/$w12 and $f13
54 ; allocator will choose $f12/$w12 for the vector and $f13 for the float to
58 ; must copy $f13 to an even-numbered register before inserting into the
[all …]
Dfmadd1.ll42 ; 64-DAG: madd.s $[[T0:f[0-9]+]], $f14, $f12, $f13
46 ; 64R2: madd.s $[[T0:f[0-9]+]], $f14, $f12, $f13
50 ; 64R6-DAG: mul.s $[[T0:f[0-9]+]], $f12, $f13
82 ; 64-DAG: msub.s $[[T0:f[0-9]+]], $f14, $f12, $f13
86 ; 64R2: msub.s $[[T0:f[0-9]+]], $f14, $f12, $f13
90 ; 64R6-DAG: mul.s $[[T0:f[0-9]+]], $f12, $f13
125 ; 64-NONAN: nmadd.s $f0, $f14, $f12, $f13
127 ; 64-NAN: madd.s $[[T0:f[0-9]+]], $f14, $f12, $f13
131 ; 64R2-NONAN: nmadd.s $f0, $f14, $f12, $f13
133 ; 64R2-NAN: madd.s $[[T0:f[0-9]+]], $f14, $f12, $f13
[all …]
Dselect.ll149 ; 64: movn.s $f14, $f13, $4
152 ; 64R2: movn.s $f14, $f13, $4
157 ; 64R6: sel.s $[[CC]], $f14, $f13
185 ; 64: movn.d $f14, $f13, $4
188 ; 64R2: movn.d $f14, $f13, $4
193 ; 64R6: sel.d $[[CC]], $f14, $f13
222 ; 64: movt.s $f13, $f12, $fcc0
223 ; 64: mov.s $f0, $f13
226 ; 64R2: movt.s $f13, $f12, $fcc0
227 ; 64R2: mov.s $f0, $f13
[all …]
Dfpbr.ll13 ; 64-FCC: c.eq.s $f12, $f13
17 ; 64-GPR: cmp.eq.s $[[FGRCC:f[0-9]+]], $f12, $f13
47 ; 64-FCC: c.olt.s $f12, $f13
51 ; 64-GPR: cmp.ule.s $[[FGRCC:f[0-9]+]], $f13, $f12
76 ; 64-FCC: c.ole.s $f12, $f13
80 ; 64-GPR: cmp.ult.s $[[FGRCC:f[0-9]+]], $f13, $f12
105 ; 64-FCC: c.eq.d $f12, $f13
109 ; 64-GPR: cmp.eq.d $[[FGRCC:f[0-9]+]], $f12, $f13
135 ; 64-FCC: c.olt.d $f12, $f13
139 ; 64-GPR: cmp.ule.d $[[FGRCC:f[0-9]+]], $f13, $f12
[all …]
Dno-odd-spreg.ll15 ; Clobber all except $f12 and $f13
18 ; allocator will choose $f12 and $f13 to avoid the spill/reload.
30 ; ODDSPREG: add.s $f13, $f12, ${{f[0-9]+}}
33 ; ODDSPREG: add.s $f0, $f12, $f13
42 ; Clobber all except $f12 and $f13
45 ; use $f12 and $f13.
Dfpxx.ll68 ; 4-NOFPXX: mov.d $f0, $f13
70 ; 64-NOFPXX: mov.d $f0, $f13
116 ; 4-NOFPXX: mov.d $f0, $f13
118 ; 64-NOFPXX: mov.d $f0, $f13
179 ; 4-NOFPXX: sub.d $f0, $f12, $f13
182 ; 64-NOFPXX: sub.d $f0, $f12, $f13
213 ; 4-NOFPXX: mov.d $f13, $f0
220 ; 64-NOFPXX: mov.d $f13, $f0
Dmips64-f128-call.ll7 ; CHECK: sdc1 $f13, 8(${{[0-9]+}})
17 ; CHECK: ldc1 $f13, 8(${{[0-9]+}})
/external/webrtc/webrtc/modules/audio_processing/aec/
Daec_rdft_mips.c272 float f0, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11, f12, f13, f14; in cft1st_128_mips() local
512 [f12] "=&f" (f12), [f13] "=&f" (f13), [f14] "=&f" (f14), in cft1st_128_mips()
521 float f0, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11, f12, f13, f14; in cftmdl_128_mips() local
631 f13 = rdft_wk3ri_first[2]; in cftmdl_128_mips()
714 [f12] "f" (f12), [f13] "f" (f13), [f14] "f" (f14) in cftmdl_128_mips()
719 f13 = rdft_wk3ri_second[2]; in cftmdl_128_mips()
801 [f12] "f" (f12), [f13] "f" (f13), [f14] "f" (f14) in cftmdl_128_mips()
929 float f1, f2, f3 ,f4, f5, f6, f7, f8, f9, f10, f11, f12, f13, f14, f15; in rftfsub_128_mips() local
1042 [f13] "=&f" (f13), [f14] "=&f" (f14), [f15] "=&f" (f15), in rftfsub_128_mips()
1056 float f1, f2, f3 ,f4, f5, f6, f7, f8, f9, f10, f11, f12, f13, f14, f15; in rftbsub_128_mips() local
[all …]
/external/v8/test/mjsunit/harmony/
Ddefault-parameters.js128 var f13 = function f(f = 7, x = f) { return x; } function in TestParameterScopingSloppy
129 assertSame(7, f13());
166 var f13 = function f(x = f) { function f() {}; return x; } function in TestParameterScopingStrict
167 assertSame(f13, f13());
189 function f13(z = eval("var y = 2"), b = eval("y")) {} function in TestSloppyEvalScoping
190 assertThrows(f13, ReferenceError);
247 function f13(z = eval("var y = 2"), b = eval("y")) {} function in TestStrictEvalScoping
248 assertThrows(f13, ReferenceError);
285 function f13(a = eval("'use strict'; x"), x = 2) { return a } function in TestParameterTDZSloppy
286 assertThrows(() => f13(), ReferenceError);
[all …]
/external/llvm/test/MC/SystemZ/
Dregs-good.s63 #CHECK: ler %f12, %f13 # encoding: [0x38,0xcd]
72 ler %f12,%f13
81 #CHECK: ldr %f12, %f13 # encoding: [0x28,0xcd]
90 ldr %f12,%f13
96 #CHECK: lxr %f12, %f13 # encoding: [0xb3,0x65,0x00,0xcd]
101 lxr %f12,%f13
132 #CHECK: .cfi_offset %f13, 232
166 .cfi_offset %f13,232
/external/llvm/test/CodeGen/SystemZ/
Dframe-07.ll20 ; CHECK-NOFP: std %f13, 4080(%r15)
28 ; CHECK-NOFP: .cfi_offset %f13, -208
37 ; CHECK-NOFP: ld %f13, 4080(%r15)
54 ; CHECK-FP: std %f13, 4080(%r11)
63 ; CHECK-FP: ld %f13, 4080(%r11)
141 ; CHECK-NOFP: stdy %f13, 524272(%r15)
149 ; CHECK-NOFP: .cfi_offset %f13, -208
158 ; CHECK-NOFP: ldy %f13, 524272(%r15)
174 ; CHECK-FP: stdy %f13, 524272(%r11)
182 ; CHECK-FP: .cfi_offset %f13, -208
[all …]
Dframe-04.ll19 ; CHECK: std %f13, 176(%r15)
27 ; CHECK: .cfi_offset %f13, -208
36 ; CHECK: ld %f13, 176(%r15)
69 ; so %f13+%f15 is the pair that gets dropped.
86 ; CHECK-NOT: %f13
134 ; CHECK-NOT: %f13
170 ; CHECK-NOT: %f13
Dframe-03.ll20 ; CHECK: std %f13, 176(%r15)
28 ; CHECK: .cfi_offset %f13, -208
37 ; CHECK: ld %f13, 176(%r15)
104 ; CHECK: std %f13, 168(%r15)
111 ; CHECK: .cfi_offset %f13, -208
120 ; CHECK: ld %f13, 168(%r15)
183 ; CHECK-NOT: %f13
230 ; CHECK-NOT: %f13
Dframe-02.ll18 ; CHECK: std %f13, 176(%r15)
26 ; CHECK: .cfi_offset %f13, -208
35 ; CHECK: ld %f13, 176(%r15)
102 ; CHECK: std %f13, 168(%r15)
109 ; CHECK: .cfi_offset %f13, -208
118 ; CHECK: ld %f13, 168(%r15)
181 ; CHECK-NOT: %f13
228 ; CHECK-NOT: %f13
Dframe-17.ll16 ; CHECK: std %f13, 184(%r15)
29 ; CHECK: ld %f13, 184(%r15)
80 ; CHECK: std %f13, 184(%r15)
90 ; CHECK: ld %f13, 184(%r15)
141 ; CHECK: std %f13, 192(%r15)
153 ; CHECK: ld %f13, 192(%r15)
/external/valgrind/VEX/priv/
Dhost_s390_isel.c1249 HReg op_hi, op_lo, f13, f15; in s390_isel_int_expr_wrk() local
1255 f13 = make_fpr(13); in s390_isel_int_expr_wrk()
1259 addInstr(env, s390_insn_move(8, f13, op_hi)); in s390_isel_int_expr_wrk()
1264 INVALID_HREG, f13, f15, in s390_isel_int_expr_wrk()
1283 HReg op_hi, op_lo, f13, f15; in s390_isel_int_expr_wrk() local
1289 f13 = make_fpr(13); in s390_isel_int_expr_wrk()
1293 addInstr(env, s390_insn_move(8, f13, op_hi)); in s390_isel_int_expr_wrk()
1298 INVALID_HREG, f13, in s390_isel_int_expr_wrk()
1351 HReg op1_hi, op1_lo, op2_hi, op2_lo, f12, f13, f14, f15, cc_s390; in s390_isel_int_expr_wrk() local
1359 f13 = make_fpr(13); in s390_isel_int_expr_wrk()
[all …]
/external/v8/test/webkit/
DtoString-elision-trailing-comma-expected.txt90 PASS f13().length is 2
91 PASS f13()[2-1] is undefined
92 PASS unevalf(eval(unevalf(f13))) is unevalf(f13)
93 PASS eval(unevalf(f13))().length is 2
94 PASS eval(unevalf(f13))()[2-1] is undefined
/external/clang/test/CodeGen/
Dfunction-attributes.c60 void f13(void) __attribute__((pure)) __attribute__((const));
61 void f13(void){} in f13() function
/external/clang/test/CXX/except/except.spec/
Dp5-virtual.cpp42 virtual void f13() noexcept(false);
78 virtual void f13() throw(int);
/external/llvm/test/Transforms/CrossDSOCFI/
Dbasic.ll54 define signext i8 @f13() {
76 !4 = !{!"_ZTSFcvE", i8 ()* @f13, i64 0}
77 !5 = !{i64 111, i8 ()* @f13, i64 0}
/external/llvm/test/CodeGen/PowerPC/
Dppc64-fastcc.ll5 …, <4 x i32> %v11, i64 %g12, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i6…
13 …, <4 x i32> %v11, i64 %g12, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i6…
21 …, <4 x i32> %v11, i64 %g12, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i6…
29 …, <4 x i32> %v11, i64 %g12, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i6…
37 …, <4 x i32> %v11, i64 %g12, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i6…
45 …, <4 x i32> %v11, i64 %g12, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i6…
53 …, <4 x i32> %v11, i64 %g12, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i6…
61 …, <4 x i32> %v11, i64 %g12, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i6…
69 …, <4 x i32> %v11, i64 %g12, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i6…
77 …, <4 x i32> %v11, i64 %g12, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i6…
[all …]
Dvsx-spill.ll10 …f1},~{f2},~{f3},~{f4},~{f5},~{f6},~{f7},~{f8},~{f9},~{f10},~{f11},~{f12},~{f13},~{f14},~{f15},~{f1…
31 …f1},~{f2},~{f3},~{f4},~{f5},~{f6},~{f7},~{f8},~{f9},~{f10},~{f11},~{f12},~{f13},~{f14},~{f15},~{f1…
51 …f1},~{f2},~{f3},~{f4},~{f5},~{f6},~{f7},~{f8},~{f9},~{f10},~{f11},~{f12},~{f13},~{f14},~{f15},~{f1…
/external/mesa3d/src/mesa/sparc/
Dnorm.S138 ld [%o3], %f13 ! LSU
145 fmuls %f3, %f13, %f3
147 fmuls %f5, %f13, %f5
149 fmuls %f7, %f13, %f7
247 ld [%o3], %f13 ! LSU
254 fmuls %f3, %f13, %f3
256 fmuls %f5, %f13, %f5
258 fmuls %f7, %f13, %f7
543 ld [%o3], %f13 ! LSU
548 fmuls %f3, %f13, %f3
[all …]

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