| /external/llvm/test/MC/Disassembler/Mips/mips64/ |
| D | valid-mips64-xfail.txt | 4 0x46 0x11 0xc5 0x32 # CHECK: c.eq.s $fcc5, $f24, $f17
10 0x46 0x0e 0x8a 0x3c # CHECK: c.lt.s $fcc2, $f17, $f14
27 0x46 0x31 0x36 0x35 # CHECK: c.ult.d $fcc6, $f6, $f17
47 0x46 0xc3 0x8e 0x37 # CHECK: c.ule.ps $fcc6, $f17, $f3
56 0x46 0xc0 0x8d 0x86 # CHECK: mov.ps $f22, $f17
60 0x46 0xdf 0x8c 0x92 # CHECK: movz.ps $f18, $f17, ra
62 0x4d 0xd1 0xeb 0x2e # CHECK: msub.ps $f12, $f14, $f29, $f17
70 0x4d 0x91 0x71 0xbe # CHECK: nmsub.ps $f6, $f12, $f14, $f17
|
| /external/llvm/test/MC/Mips/mips3/ |
| D | invalid-mips5-wrong-error.s | 25 c.ule.ps $fcc6,$f17,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
32 mov.ps $f22,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
36 movz.ps $f18,$f17,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
37 msub.ps $f12,$f14,$f29,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
41 nmsub.ps $f6,$f12,$f14,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
|
| /external/llvm/test/MC/Mips/mips4/ |
| D | invalid-mips5-wrong-error.s | 25 c.ule.ps $fcc6,$f17,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
32 mov.ps $f22,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
36 movz.ps $f18,$f17,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
37 msub.ps $f12,$f14,$f29,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
41 nmsub.ps $f6,$f12,$f14,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
|
| /external/llvm/test/MC/Mips/mips2/ |
| D | invalid-mips5-wrong-error.s | 25 c.ule.ps $fcc6,$f17,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
32 mov.ps $f22,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
36 movz.ps $f18,$f17,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
37 msub.ps $f12,$f14,$f29,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
41 nmsub.ps $f6,$f12,$f14,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
|
| /external/llvm/test/MC/Mips/mips1/ |
| D | invalid-mips5-wrong-error.s | 25 c.ule.ps $fcc6,$f17,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
32 mov.ps $f22,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
36 movz.ps $f18,$f17,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
37 msub.ps $f12,$f14,$f29,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
41 nmsub.ps $f6,$f12,$f14,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
|
| /external/llvm/test/MC/Mips/mips64r6/ |
| D | invalid-mips5-wrong-error.s | 28 … c.ule.ps $fcc6,$f17,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
34 … mov.ps $f22,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
38 … movz.ps $f18,$f17,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
39 … msub.ps $f12,$f14,$f29,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
43 … nmsub.ps $f6,$f12,$f14,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
|
| /external/clang/test/CodeGen/ |
| D | function-attributes.c | 85 __attribute__ ((returns_twice)) void f17(void);
87 f17(); in f18()
|
| D | regparm-struct.c | 161 __attribute__((regparm(3))) struct s12 f17(int a, int b, int c);
164 f17(41, 42, 43); in g17()
|
| /external/clang/test/CXX/except/except.spec/ |
| D | p3.cpp | 77 void f17();
78 void f17() noexcept(false);
|
| /external/llvm/test/MC/Disassembler/Mips/mips32/ |
| D | valid-xfail-mips32.txt | 4 0x46 0x11 0xc5 0x32 # CHECK: c.eq.s $fcc5, $f24, $f17
10 0x46 0x0e 0x8a 0x3c # CHECK: c.lt.s $fcc2, $f17, $f14
27 0x46 0x31 0x36 0x35 # CHECK: c.ult.d $fcc6, $f6, $f17
|
| /external/llvm/test/CodeGen/PowerPC/ |
| D | vsx-spill.ll | 10 …~{f6},~{f7},~{f8},~{f9},~{f10},~{f11},~{f12},~{f13},~{f14},~{f15},~{f16},~{f17},~{f18},~{f19},~{f2…
31 …~{f6},~{f7},~{f8},~{f9},~{f10},~{f11},~{f12},~{f13},~{f14},~{f15},~{f16},~{f17},~{f18},~{f19},~{f2…
51 …~{f6},~{f7},~{f8},~{f9},~{f10},~{f11},~{f12},~{f13},~{f14},~{f15},~{f16},~{f17},~{f18},~{f19},~{f2…
|
| /external/llvm/test/MC/Disassembler/Mips/mips4/ |
| D | valid-xfail-mips4.txt | 4 0x46 0x11 0xc5 0x32 # CHECK: c.eq.s $fcc5, $f24, $f17
10 0x46 0x0e 0x8a 0x3c # CHECK: c.lt.s $fcc2, $f17, $f14
27 0x46 0x31 0x36 0x35 # CHECK: c.ult.d $fcc6, $f6, $f17
|
| /external/valgrind/none/tests/ppc64/ |
| D | test_isa_2_06_part2.c | 56 register double f17 __asm__ ("fr17");
1051 __asm__ __volatile__ ("fctiduz. %0, %1" : "=d" (f17) : "d" (f14)); in test_fctiduz()
1053 __asm__ __volatile__ ("fctiduz %0, %1" : "=d" (f17) : "d" (f14)); in test_fctiduz()
1059 __asm__ __volatile__ ("fctidu. %0, %1" : "=d" (f17) : "d" (f14)); in test_fctidu()
1061 __asm__ __volatile__ ("fctidu %0, %1" : "=d" (f17) : "d" (f14)); in test_fctidu()
1067 __asm__ __volatile__ ("fctiwuz. %0, %1" : "=d" (f17) : "d" (f14)); in test_fctiwuz()
1069 __asm__ __volatile__ ("fctiwuz %0, %1" : "=d" (f17) : "d" (f14)); in test_fctiwuz()
1075 __asm__ __volatile__ ("fctiwu. %0, %1" : "=d" (f17) : "d" (f14)); in test_fctiwu()
1077 __asm__ __volatile__ ("fctiwu %0, %1" : "=d" (f17) : "d" (f14)); in test_fctiwu()
1708 result = f17; in test_fct_ops()
|
| D | test_dfp3.c | 33 register double f17 __asm__ ("fr17");
833 f17 = d0x; in test_dfp_quai_ops()
901 f17 = d1x; in test_dfp_qua_ops()
960 f17 = d0x; in test_dfp_rrnd_ops()
1042 f17 = d0x; in test_dfp_xiex_ops()
1119 f17 = d0x; in test_dfp_rint_ops()
1198 f17 = d1x; in test_dfp_cmp_ops()
|
| D | test_isa_2_06_part1.c | 51 register double f17 __asm__ ("fr17");
1202 __asm__ __volatile__ ("fcfids %0, %1" : "=f" (f17): "d" (f14)); in test_fcfids()
1207 __asm__ __volatile__ ("fcfidus %0, %1" : "=f" (f17): "d" (f14)); in test_fcfidus()
1212 __asm__ __volatile__ ("fcfidu %0, %1" : "=f" (f17): "d" (f14)); in test_fcfidu()
1882 res = f17; in test_p7_fpops()
1886 resd = f17; in test_p7_fpops()
|
| /external/valgrind/none/tests/ppc32/ |
| D | test_isa_2_06_part2.c | 56 register double f17 __asm__ ("fr17");
1051 __asm__ __volatile__ ("fctiduz. %0, %1" : "=d" (f17) : "d" (f14)); in test_fctiduz()
1053 __asm__ __volatile__ ("fctiduz %0, %1" : "=d" (f17) : "d" (f14)); in test_fctiduz()
1059 __asm__ __volatile__ ("fctidu. %0, %1" : "=d" (f17) : "d" (f14)); in test_fctidu()
1061 __asm__ __volatile__ ("fctidu %0, %1" : "=d" (f17) : "d" (f14)); in test_fctidu()
1067 __asm__ __volatile__ ("fctiwuz. %0, %1" : "=d" (f17) : "d" (f14)); in test_fctiwuz()
1069 __asm__ __volatile__ ("fctiwuz %0, %1" : "=d" (f17) : "d" (f14)); in test_fctiwuz()
1075 __asm__ __volatile__ ("fctiwu. %0, %1" : "=d" (f17) : "d" (f14)); in test_fctiwu()
1077 __asm__ __volatile__ ("fctiwu %0, %1" : "=d" (f17) : "d" (f14)); in test_fctiwu()
1708 result = f17; in test_fct_ops()
|
| D | test_dfp3.c | 33 register double f17 __asm__ ("fr17");
833 f17 = d0x; in test_dfp_quai_ops()
901 f17 = d1x; in test_dfp_qua_ops()
960 f17 = d0x; in test_dfp_rrnd_ops()
1042 f17 = d0x; in test_dfp_xiex_ops()
1119 f17 = d0x; in test_dfp_rint_ops()
1198 f17 = d1x; in test_dfp_cmp_ops()
|
| D | test_isa_2_06_part1.c | 51 register double f17 __asm__ ("fr17");
1202 __asm__ __volatile__ ("fcfids %0, %1" : "=f" (f17): "d" (f14)); in test_fcfids()
1207 __asm__ __volatile__ ("fcfidus %0, %1" : "=f" (f17): "d" (f14)); in test_fcfidus()
1212 __asm__ __volatile__ ("fcfidu %0, %1" : "=f" (f17): "d" (f14)); in test_fcfidu()
1882 res = f17; in test_p7_fpops()
1886 resd = f17; in test_p7_fpops()
|
| /external/llvm/test/CodeGen/Mips/ |
| D | no-odd-spreg-msa.ll | 26 …f5},~{$f6},~{$f7},~{$f8},~{$f9},~{$f10},~{$f11},~{$f14},~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{…
60 …f5},~{$f6},~{$f7},~{$f8},~{$f9},~{$f10},~{$f11},~{$f14},~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{…
90 …f5},~{$f6},~{$f7},~{$f8},~{$f9},~{$f10},~{$f11},~{$f14},~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{…
118 …6},~{$f7},~{$f8},~{$f9},~{$f10},~{$f11},~{$f12},~{$f14},~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{…
|
| D | no-odd-spreg.ll | 24 …f5},~{$f6},~{$f7},~{$f8},~{$f9},~{$f10},~{$f11},~{$f14},~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{…
48 …f5},~{$f6},~{$f7},~{$f8},~{$f9},~{$f10},~{$f11},~{$f14},~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{…
|
| /external/llvm/test/MC/ARM/ |
| D | symbol-variants.s | 59 .word f17(target2)
61 @CHECK: 44 R_ARM_TARGET2 f17
|
| /external/libjpeg-turbo/simd/ |
| D | jsimd_mips_dspr2_asm.h | 76 #define f17 $f17 macro
|
| /external/compiler-rt/lib/builtins/ppc/ |
| D | saveFP.S | 24 stfd f17,-120(r1)
|
| D | restFP.S | 26 lfd f17,-120(r1)
|
| /external/clang/test/SemaObjCXX/ |
| D | nullability-pragmas.mm | 30 f17(a); // expected-error{{no matching function for call to 'f17'}}
|