| /external/llvm/test/CodeGen/AArch64/ |
| D | fp16-v16-instructions.ll | 10 ; CHECK-DAG: fcvtn v0.4h, [[S0]]
11 ; CHECK-DAG: fcvtn v1.4h, [[S2]]
33 ; CHECK-DAG: fcvtn [[S0:v[0-9]+]].2s, [[D0]]
34 ; CHECK-DAG: fcvtn [[S1:v[0-9]+]].2s, [[D2]]
35 ; CHECK-DAG: fcvtn [[S2:v[0-9]+]].2s, [[D4]]
36 ; CHECK-DAG: fcvtn [[S3:v[0-9]+]].2s, [[D6]]
43 ; CHECK-DAG: fcvtn v0.4h, [[S0]].4s
44 ; CHECK-DAG: fcvtn v1.4h, [[S2]].4s
45 ; CHECK-DAG: fcvtn v[[R1:[0-9]+]].4h, [[S1]].4s
46 ; CHECK-DAG: fcvtn v[[R3:[0-9]+]].4h, [[S3]].4s
[all …]
|
| D | fp16-v8-instructions.ll | 182 ; CHECK-DAG: fcvtn v0.4h, v0.4s
183 ; CHECK-DAG: fcvtn [[REG:v[0-9+]]].4h, v1.4s
264 ; CHECK-DAG: fcvtn v[[LOREG:[0-9]+]].4h, [[LOF]]
265 ; CHECK-DAG: fcvtn v0.4h, [[HIF]]
278 ; CHECK-DAG: fcvtn v[[LOREG:[0-9]+]].4h, [[LOF]]
279 ; CHECK-DAG: fcvtn v0.4h, [[HIF]]
290 ; CHECK-DAG: fcvtn v[[REG:[0-9]+]].4h, [[OP2]]
291 ; CHECK-DAG: fcvtn v0.4h, [[OP1]]
302 ; CHECK-DAG: fcvtn [[OP3:v[0-9]+]].2s, [[OP1]]
304 ; CHECK: fcvtn v0.4h, [[OP3]].4s
[all …]
|
| D | fp16-v4-instructions.ll | 9 ; CHECK: fcvtn v0.4h, [[RES]]
30 ; CHECK: fcvtn v0.4h, [[RES]]
42 ; CHECK: fcvtn v0.4h, [[RES]]
54 ; CHECK: fcvtn v0.4h, [[RES]]
79 ; CHECK: fcvtn v0.4h, v0.4s
139 ; CHECK-NEXT: fcvtn v0.4h, [[OP4]]
150 ; CHECK-NEXT: fcvtn v0.4h, [[OP2]]
160 ; CHECK-NEXT: fcvtn v0.4h, [[OP1]]
170 ; CHECK-DAG: fcvtn [[OP3:v[0-9]+]].2s, [[OP1]]
172 ; CHECK-NEXT: fcvtn v0.4h, [[OP3]].4s
[all …]
|
| D | arm64-convert-v4f64.ll | 38 ; CHECK-DAG: fcvtn v[[MID:[0-9]+]].2s, v[[LHS]].2d
40 ; CHECK: fcvtn v0.4h, v[[MID]].4s
|
| D | complex-int-to-fp.ll | 76 ; CHECK: fcvtn v0.2s, [[VAL64]].2d
84 ; CHECK: fcvtn v0.2s, [[VAL64]].2d
|
| D | arm64-vcvt_f32_su32.ll | 57 ; CHECK: fcvtn v0.4h, v0.4s
|
| D | arm64-vcvt_f.ll | 24 ; CHECK: fcvtn
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| D | fdiv_combine.ll | 98 ; CHECK: fcvtn v0.2s, v0.2d
|
| D | vector-fcopysign.ll | 71 ; CHECK-NEXT: fcvtn v1.2s, v1.2d
|
| /external/llvm/test/MC/AArch64/ |
| D | neon-simd-misc.s | 425 fcvtn v13.4h, v21.4s
426 fcvtn v4.2s, v0.2d
|
| D | arm64-advsimd.s | 862 fcvtn v2.4h, v4.4s
863 fcvtn v3.2s, v5.2d
869 ; CHECK: fcvtn v2.4h, v4.4s ; encoding: [0x82,0x68,0x21,0x0e]
870 ; CHECK: fcvtn v3.2s, v5.2d ; encoding: [0xa3,0x68,0x61,0x0e]
|
| D | neon-diagnostics.s | 5798 fcvtn v2.8h, v4.4s
5799 fcvtn v6.4s, v8.2d
|
| /external/llvm/test/MC/Disassembler/AArch64/ |
| D | arm64-advsimd.txt | 559 # CHECK: fcvtn v0.4h, v0.4s
561 # CHECK: fcvtn v0.2s, v0.2d
|
| /external/vixl/src/vixl/a64/ |
| D | simulator-a64.h | 2347 LogicVRegister fcvtn(VectorFormat vform,
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| D | macro-assembler-a64.h | 1204 fcvtn(vd, vn); in Fcvtn()
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| D | assembler-a64.h | 2180 void fcvtn(const VRegister& vd, const VRegister& vn);
|
| D | simulator-a64.cc | 2496 fcvtn(vf_fcvtn, rd, rn); in VisitNEON2RegMisc()
|
| D | logic-a64.cc | 4465 LogicVRegister Simulator::fcvtn(VectorFormat vform, in fcvtn() function in vixl::Simulator
|
| D | assembler-a64.cc | 2820 void Assembler::fcvtn(const VRegister& vd, in fcvtn() function in vixl::Assembler
|
| /external/vixl/test/ |
| D | test-simulator-a64.cc | 3947 DEFINE_TEST_NEON_2DIFF_FP_NARROW(fcvtn, Conversions) in DEFINE_TEST_NEON_2DIFF_FP_SCALAR_SD()
|
| /external/vixl/doc/ |
| D | supported-instructions.md | 1962 void fcvtn(const VRegister& vd, const VRegister& vn)
|
| /external/valgrind/none/tests/arm64/ |
| D | fp_and_simd.stdout.exp | 26688 fcvtn v22.4h, v23.4s 3e80398f54c6346f38686a10aa85e392 a0d83ef4380b82357abee438e0a3a204 0000000…
26690 fcvtn v22.2s, v23.2d 8779cc5b2a997db3d694043bcd86849b 0ab84637730d826f0b5ee27312980014 0000000…
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.td | 2729 defm FCVTN : SIMDFPNarrowTwoVector<0, 0, 0b10110, "fcvtn">;
|