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Searched refs:fcvtps (Results 1 – 21 of 21) sorted by relevance

/external/llvm/test/MC/AArch64/
Dneon-scalar-cvt.s169 fcvtps h22, h13
170 fcvtps s22, s13
171 fcvtps d21, d14
Darm64-fp-encoding.s362 fcvtps w1, h2
363 fcvtps w1, s2
364 fcvtps w1, d2
365 fcvtps x1, h2
366 fcvtps x1, s2
367 fcvtps x1, d2
369 ; FP16: fcvtps w1, h2 ; encoding: [0x41,0x00,0xe8,0x1e]
371 ; NO-FP16-NEXT: fcvtps w1, h2
372 ; CHECK: fcvtps w1, s2 ; encoding: [0x41,0x00,0x28,0x1e]
373 ; CHECK: fcvtps w1, d2 ; encoding: [0x41,0x00,0x68,0x1e]
[all …]
Dneon-simd-misc.s573 fcvtps v4.4h, v0.4h
574 fcvtps v6.8h, v8.8h
575 fcvtps v6.4s, v8.4s
576 fcvtps v6.2d, v8.2d
577 fcvtps v4.2s, v0.2s
Dfullfp16-neon-neg.s242 fcvtps h22, h13
338 fcvtps v4.4h, v0.4h
340 fcvtps v6.8h, v8.8h
Darm64-advsimd.s876 fcvtps.2s v0, v0
877 fcvtps.4s v0, v0
878 fcvtps.2d v0, v0
879 fcvtps s0, s0
880 fcvtps d0, d0 define
882 ; CHECK: fcvtps.2s v0, v0 ; encoding: [0x00,0xa8,0xa1,0x0e]
883 ; CHECK: fcvtps.4s v0, v0 ; encoding: [0x00,0xa8,0xa1,0x4e]
884 ; CHECK: fcvtps.2d v0, v0 ; encoding: [0x00,0xa8,0xe1,0x4e]
885 ; CHECK: fcvtps s0, s0 ; encoding: [0x00,0xa8,0xa1,0x5e]
886 ; CHECK: fcvtps d0, d0 ; encoding: [0x00,0xa8,0xe1,0x5e]
Dneon-diagnostics.s5901 fcvtps v0.16b, v31.16b
5902 fcvtps v2.8h, v4.8h
5903 fcvtps v1.8b, v9.8b
5904 fcvtps v13.4h, v21.4h
7267 fcvtps s0, d0
7268 fcvtps d0, s0 define
Dbasic-a64-instructions.s2077 fcvtps wzr, s9
2078 fcvtps x12, s20
2131 fcvtps wzr, d9
2132 fcvtps x12, d20
/external/llvm/test/CodeGen/AArch64/
Darm64-cvt.ll248 ;CHECK: fcvtps w0, s0
250 %tmp3 = call i32 @llvm.aarch64.neon.fcvtps.i32.f32(float %A)
256 ;CHECK: fcvtps x0, s0
258 %tmp3 = call i64 @llvm.aarch64.neon.fcvtps.i64.f32(float %A)
264 ;CHECK: fcvtps w0, d0
266 %tmp3 = call i32 @llvm.aarch64.neon.fcvtps.i32.f64(double %A)
272 ;CHECK: fcvtps x0, d0
274 %tmp3 = call i64 @llvm.aarch64.neon.fcvtps.i64.f64(double %A)
278 declare i32 @llvm.aarch64.neon.fcvtps.i32.f32(float) nounwind readnone
279 declare i64 @llvm.aarch64.neon.fcvtps.i64.f32(float) nounwind readnone
[all …]
Dround-conv.ll84 ; CHECK: fcvtps w0, s0
94 ; CHECK: fcvtps x0, s0
104 ; CHECK: fcvtps w0, d0
114 ; CHECK: fcvtps x0, d0
Darm64-vcvt.ll130 ;CHECK: fcvtps.2s v0, v0
132 %tmp3 = call <2 x i32> @llvm.aarch64.neon.fcvtps.v2i32.v2f32(<2 x float> %A)
139 ;CHECK: fcvtps.4s v0, v0
141 %tmp3 = call <4 x i32> @llvm.aarch64.neon.fcvtps.v4i32.v4f32(<4 x float> %A)
148 ;CHECK: fcvtps.2d v0, v0
150 %tmp3 = call <2 x i64> @llvm.aarch64.neon.fcvtps.v2i64.v2f64(<2 x double> %A)
154 declare <2 x i32> @llvm.aarch64.neon.fcvtps.v2i32.v2f32(<2 x float>) nounwind readnone
155 declare <4 x i32> @llvm.aarch64.neon.fcvtps.v4i32.v4f32(<4 x float>) nounwind readnone
156 declare <2 x i64> @llvm.aarch64.neon.fcvtps.v2i64.v2f64(<2 x double>) nounwind readnone
/external/llvm/test/MC/Disassembler/AArch64/
Dbasic-a64-instructions.txt1701 # FP16: fcvtps wzr, h9
1702 # FP16: fcvtps x12, h20
1755 # CHECK: fcvtps wzr, s9
1756 # CHECK: fcvtps x12, s20
1809 # CHECK: fcvtps wzr, d9
1810 # CHECK: fcvtps x12, d20
Dneon-instructions.txt2600 # CHECK: fcvtps s22, s13
2601 # CHECK: fcvtps d21, d14
Darm64-advsimd.txt476 # CHECK: fcvtps.2s v0, v0
/external/vixl/src/vixl/a64/
Dmacro-assembler-a64.h1261 fcvtps(rd, vn); in Fcvtps()
2266 V(fcvtps, Fcvtps) \
Dassembler-a64.h2240 void fcvtps(const Register& rd, const VRegister& vn);
2246 void fcvtps(const VRegister& vd, const VRegister& vn);
Dassembler-a64.cc2863 V(fcvtps, NEON_FCVTPS, FCVTPS) \
/external/vixl/test/
Dtest-simulator-a64.cc3961 DEFINE_TEST_NEON_2SAME_FP(fcvtps, Conversions) in DEFINE_TEST_NEON_2DIFF_FP_SCALAR_SD()
4012 DEFINE_TEST_NEON_2SAME_FP_SCALAR(fcvtps, Conversions) in DEFINE_TEST_NEON_2DIFF_FP_SCALAR_SD()
Dtest-disasm-a64.cc2471 COMPARE(fcvtps(x28, d29), "fcvtps x28, d29"); in TEST()
2472 COMPARE(fcvtps(w30, d31), "fcvtps w30, d31"); in TEST()
2475 COMPARE(fcvtps(x4, s5), "fcvtps x4, s5"); in TEST()
2476 COMPARE(fcvtps(w6, s7), "fcvtps w6, s7"); in TEST()
/external/vixl/doc/
Dsupported-instructions.md2004 void fcvtps(const Register& rd, const VRegister& vn)
2011 void fcvtps(const VRegister& vd, const VRegister& vn)
/external/valgrind/none/tests/arm64/
Dfp_and_simd.stdout.exp26747 fcvtps d10, d21 12b5ac7cebf0223aec026528f9bc9e80 1cf114e102e4bd3376c767248e4526f2 0000000000000…
26749 fcvtps s10, s21 125db279db409294f44d8a9c379a9670 24320f44de253f6500cdead09216f96c 0000000000000…
26751 fcvtps v10.2d, v21.2d 9f5a2abd80ab5cbc5afc70e7faa338c0 19a6dbd0d062794548168f357cf3d626 0000000…
26753 fcvtps v10.4s, v21.4s baaa1348db327fb51e0e180943d8836f fb4f7982d79a6ed64da255504cdbbd1e 8000000…
26755 fcvtps v10.2s, v21.2s 624d6e1cebd5fc7d3f8381041239787d cb2ae85cf4ce1c1510723c2301cfad57 0000000…
26757 fcvtps w21, s10 98443b36b193d214bd5cacd566c416eb 893a295e27fe8305908645ae9ccea6ce 98443b36b193d…
26759 fcvtps x21, s10 5b8e79982d6c027b9999997f3f7c5eb8 347c3b876f29a4a3cedd70f01cd9a986 5b8e79982d6c0…
26761 fcvtps w21, d10 ac2c28425d628bb1d33947ff9e5e4fe5 cdf21fd8cc4f7ff2c977bcea82efb57d ac2c28425d628…
26763 fcvtps x21, d10 8b1d493344726eb76a3cb658836dea71 539cd4503f7113ef82552a9bcd11cbb3 8b1d493344726…
/external/llvm/lib/Target/AArch64/
DAArch64InstrInfo.td2441 defm FCVTPS : FPToIntegerUnscaled<0b01, 0b000, "fcvtps", int_aarch64_neon_fcvtps>;
2739 defm FCVTPS : SIMDTwoVectorFPToInt<0,1,0b11010, "fcvtps",int_aarch64_neon_fcvtps>;
3273 defm FCVTPS : SIMDFPTwoScalar< 0, 1, 0b11010, "fcvtps">;