| /external/llvm/test/MC/AArch64/ |
| D | arm64-fp-encoding.s | 538 fmov h1, w2
539 fmov w1, h2
540 fmov h1, x2
541 fmov x1, h2
542 fmov s1, w2
543 fmov w1, s2
544 fmov d1, x2 define
545 fmov x1, d2
547 ; FP16: fmov h1, w2 ; encoding: [0x41,0x00,0xe7,0x1e]
549 ; NO-FP16-NEXT: fmov h1, w2
[all …]
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| D | arm64-fp-encoding-error.s | 3 fmov s0, #-0.0
6 fmov d0, #-0.0 define
|
| D | arm64-optional-hash.s | 16 ; CHECK: fmov s1, #0.12500000 ; encoding: [0x01,0x10,0x28,0x1e]
17 fmov s1, 0.125 label
|
| D | neon-mov.s | 186 fmov v1.2s, #1.0
187 fmov v15.4s, #1.0
188 fmov v31.2d, #1.0
|
| /external/llvm/test/CodeGen/AArch64/ |
| D | arm64-fast-isel-materialize.ll | 3 ; Materialize using fmov
6 ; CHECK: fmov s0, #1.25000000
12 ; CHECK: fmov s0, wzr
18 ; CHECK: fmov d0, #1.25000000
24 ; CHECK: fmov d0, xzr
|
| D | arm64-fcmp-opt.ll | 45 ; CHECK-DAG: fmov s[[ONE:[0-9]+]], #1.0
57 ; CHECK-DAG: fmov s[[ONE:[0-9]+]], #1.0
69 ; CHECK-DAG: fmov s[[ONE:[0-9]+]], #1.0
81 ; CHECK-DAG: fmov s[[ONE:[0-9]+]], #1.0
93 ; CHECK-DAG: fmov s[[ONE:[0-9]+]], #1.0
105 ; CHECK-DAG: fmov s[[ONE:[0-9]+]], #1.0
116 ; CHECK-DAG: fmov s[[ONE:[0-9]+]], #1.0
127 ; CHECK-DAG: fmov s[[ONE:[0-9]+]], #1.0
138 ; CHECK-DAG: fmov s[[ONE:[0-9]+]], #1.0
149 ; CHECK-DAG: fmov s[[ONE:[0-9]+]], #1.0
[all …]
|
| D | arm64-popcnt.ll | 8 ; CHECK: fmov d0, x[[IN64]]
11 ; CHECK: fmov w0, s0
25 ; CHECK: fmov w0, s0
26 ; CHECK: fmov d0, x0
29 ; CHECK: fmov w0, s0
42 ; CHECK: fmov d0, x0
45 ; CHECK: fmov w0, s0
|
| D | arm64-neon-select_cc.ll | 6 ; CHECK-DAG: fmov s[[LHS:[0-9]+]], w0
7 ; CHECK-DAG: fmov s[[RHS:[0-9]+]], w1
37 ; CHECK-DAG: fmov s[[LHS:[0-9]+]], w0
38 ; CHECK-DAG: fmov s[[RHS:[0-9]+]], w1
69 ; CHECK-DAG: fmov s[[LHS:[0-9]+]], w0
70 ; CHECK-DAG: fmov s[[RHS:[0-9]+]], w1
81 ; CHECK-DAG: fmov s[[LHS:[0-9]+]], w0
82 ; CHECK-DAG: fmov s[[RHS:[0-9]+]], w1
93 ; CHECK-DAG: fmov s[[LHS:[0-9]+]], w0
94 ; CHECK-DAG: fmov s[[RHS:[0-9]+]], w1
[all …]
|
| D | arm64-AdvSIMD-Scalar.ll | 13 ; CHECK-NOOPT: fmov [[COPY_REG3:x[0-9]+]], d[[REG3]]
16 ; CHECK-OPT-NOT: fmov
17 ; CHECK: fmov [[COPY_REG2:x[0-9]+]], d[[REG2]]
18 ; CHECK-NOOPT: fmov d0, [[COPY_REG3]]
19 ; CHECK-OPT-NOT: fmov
27 ; GENERIC-NOOPT: fmov [[COPY_REG3:x[0-9]+]], d[[REG3]]
28 ; GENERIC-OPT-NOT: fmov
29 ; GENERIC: fmov [[COPY_REG2:x[0-9]+]], d[[REG2]]
30 ; GENERIC-NOOPT: fmov d0, [[COPY_REG3]]
31 ; GENERIC-OPT-NOT: fmov
|
| D | fpimm.ll | 14 ; CHECK-DAG: fmov [[EIGHT5:s[0-9]+]], #8.5
30 ; CHECK-DAG: fmov {{d[0-9]+}}, #8.5
43 ; LARGE-NEXT: fmov s0, [[REG]]
53 ; LARGE-NEXT: fmov d0, [[REG]]
|
| D | remat-float0.ll | 3 ; Check that float 0 gets rematerialized with an fmov of zero reg instead
10 ; CHECK: fmov s0, wzr
12 ; CHECK: fmov s0, wzr
|
| D | arm64-vecCmpBr.ll | 10 ; CHECK-NEXT: fmov w[[REGNO2:[0-9]+]], s[[REGNO1]]
35 ; CHECK-NEXT: fmov w[[REGNO2:[0-9]+]], s[[REGNO1]]
59 ; CHECK-NEXT: fmov w[[REGNO2:[0-9]+]], s[[REGNO1]]
83 ; CHECK-NEXT: fmov w[[REGNO2:[0-9]+]], s[[REGNO1]]
106 ; CHECK-NEXT: fmov w[[REGNO2:[0-9]+]], s[[REGNO1]]
129 ; CHECK-NEXT: fmov w[[REGNO2:[0-9]+]], s[[REGNO1]]
152 ; CHECK-NEXT: fmov w[[REGNO2:[0-9]+]], s[[REGNO1]]
175 ; CHECK-NEXT: fmov w[[REGNO2:[0-9]+]], s[[REGNO1]]
|
| D | arm64-crypto.ll | 45 ; CHECK: fmov [[HASH_E:s[0-9]+]], w0
54 ; CHECK: fmov [[HASH_E:s[0-9]+]], w0
56 ; CHECK-NOT: fmov
66 ; CHECK: fmov [[HASH_E:s[0-9]+]], w0
74 ; CHECK: fmov [[HASH_E:s[0-9]+]], w0
82 ; CHECK: fmov [[HASH_E:s[0-9]+]], w0
84 ; CHECK: fmov w0, [[RES]]
|
| D | arm64-vaddv.ll | 53 ; CHECK-NEXT: fmov w0, s[[REGNUM]]
74 ; CHECK-NEXT: fmov x0, [[REGNUM]]
95 ; CHECK-NEXT: fmov w0, s[[REGNUM]]
118 ; CHECK-NEXT: fmov w0, s[[REGNUM]]
129 ; CHECK-NEXT: fmov w0, s[[REGNUM]]
152 ; CHECK-NEXT: fmov w0, s[[REGNUM]]
164 ; CHECK-NEXT: fmov w0, s[[REGNUM]]
213 ; CHECK-NEXT: fmov x0, [[REGNUM]]
234 ; CHECK-NOT: fmov
292 ; CHECK-NEXT: fmov w0, [[REGNUM]]
[all …]
|
| D | arm64-reg-copy-noneon.ll | 5 ;CHECK: fmov s0, s1
11 ;CHECK: fmov d0, d1
|
| D | arm64-2012-05-07-DAGCombineVectorExtract.ll | 5 ; CHECK: fmov w0, s0
14 ; CHECK: fmov x0, d0
|
| D | fcvt-int.ll | 123 ; CHECK: fmov {{w[0-9]+}}, {{s[0-9]+}}
131 ; CHECK: fmov {{x[0-9]+}}, {{d[0-9]+}}
139 ; CHECK: fmov {{s[0-9]+}}, {{w[0-9]+}}
148 ; CHECK: fmov {{d[0-9]+}}, {{x[0-9]+}}
|
| D | arm64-vaddlv.ll | 6 ; CHECK-NEXT: fmov x[[OUTREG:[0-9]+]], d[[REGNUM]]
16 ; CHECK-NEXT: fmov x[[OUTREG:[0-9]+]], d[[REGNUM]]
|
| D | fp-cond-sel.ll | 16 ; CHECK: fmov s[[FLT1:[0-9]+]], #1.0
24 ; CHECK: fmov d[[FLT1:[0-9]+]], #1.0
|
| D | arm64-zero-cycle-zeroing.ll | 8 ; CHECK-NOT: fmov
39 ; CHECK-NOT: fmov
|
| D | fpconv-vector-op-scalarize.ll | 31 ; CHECK-NEXT: fmov d0, x0
40 ; CHECK-NEXT: fmov d0, x0
|
| D | func-calls.ll | 93 ; CHECK-DAG: fmov d[[FINAL_DOUBLE:[0-9]+]], #1.0
97 ; CHECK-NONEON-DAG: fmov d[[FINAL_DOUBLE:[0-9]+]], #1.0
98 ; CHECK-NONEON: fmov d0, d[[FINAL_DOUBLE]]
101 ; CHECK-NOFP-NOT: fmov
|
| D | arm64-uminv.ll | 6 ; CHECK: fmov [[REG2:w[0-9]+]], s[[REG]]
29 ; CHECK: fmov [[REG2:w[0-9]+]], s[[REG]]
50 ; CHECK: fmov [[REG2:w[0-9]+]], s[[REG]]
71 ; CHECK: fmov [[REG2:w[0-9]+]], s[[REG]]
|
| /external/llvm/test/MC/Disassembler/AArch64/ |
| D | arm64-scalar-fp.txt | 226 # FP16: fmov h1, w2
227 # FP16: fmov w1, h2
228 # CHECK: fmov s1, w2
229 # CHECK: fmov w1, s2
230 # CHECK: fmov d1, x2
231 # CHECK: fmov x1, d2
239 # FP16: fmov h1, #0.12500000
240 # CHECK: fmov s1, #0.12500000
241 # CHECK: fmov d1, #0.12500000
242 # CHECK: fmov d1, #-0.48437500
[all …]
|
| D | arm64-non-apple-fmov.txt | 6 # CHECK: fmov x0, v0.d[1]
7 # CHECK: fmov v0.d[1], x0
|