Searched refs:getCondCode (Results 1 – 9 of 9) sorted by relevance
| /external/llvm/lib/Target/AMDGPU/ |
| D | R600ISelLowering.cpp | 1086 DAG.getCondCode(ISD::SETNE) in LowerFPTOUINT()
1155 CC = DAG.getCondCode(InverseCC); in LowerSELECT_CC()
1161 CC = DAG.getCondCode(SwapInvCC); in LowerSELECT_CC()
1189 CC = DAG.getCondCode(CCSwapped); in LowerSELECT_CC()
1197 CC = DAG.getCondCode(CCSwapped); in LowerSELECT_CC()
1229 DAG.getCondCode(CCOpcode)); in LowerSELECT_CC()
1255 DAG.getCondCode(ISD::SETNE)); in LowerSELECT_CC()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeFloatTypes.cpp | 863 DAG.getCondCode(CCCode), NewLHS, NewRHS, in SoftenFloatOp_BR_CC()
916 DAG.getCondCode(CCCode)), in SoftenFloatOp_SELECT_CC()
938 DAG.getCondCode(CCCode)), in SoftenFloatOp_SETCC()
1560 DAG.getCondCode(CCCode), NewLHS, NewRHS, in ExpandFloatOp_BR_CC()
1656 DAG.getCondCode(CCCode)), 0); in ExpandFloatOp_SELECT_CC()
1673 DAG.getCondCode(CCCode)), 0); in ExpandFloatOp_SETCC()
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| D | LegalizeIntegerTypes.cpp | 2775 LHSHi, RHSHi, DAG.getCondCode(CCCode)); in IntegerExpandSetCCOperands()
2829 LHSHi, RHSHi, LowCmp.getValue(1), DAG.getCondCode(CCCode)); in IntegerExpandSetCCOperands()
2860 DAG.getCondCode(CCCode), NewLHS, NewRHS, in ExpandIntOp_BR_CC()
2879 DAG.getCondCode(CCCode)), 0); in ExpandIntOp_SELECT_CC()
2896 DAG.getCondCode(CCCode)), 0); in ExpandIntOp_SETCC()
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| D | LegalizeDAG.cpp | 1837 CC = DAG.getCondCode(InvCC); in LegalizeSetCCCondCode()
1888 CC = DAG.getCondCode(InvCC); in LegalizeSetCCCondCode()
3757 DAG.getCondCode(ISD::SETNE), Tmp3, in ExpandNode()
3871 CC = DAG.getCondCode(ISD::SETNE); in ExpandNode()
3902 Tmp4 = DAG.getCondCode(ISD::SETNE); in ExpandNode()
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| D | TargetLowering.cpp | 224 NewLHS, NewRHS, DAG.getCondCode(CCCode)); in softenSetCCOperands()
230 NewLHS, NewRHS, DAG.getCondCode(getCmpLibcallCC(LC2))); in softenSetCCOperands()
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| D | SelectionDAG.cpp | 1475 SDValue SelectionDAG::getCondCode(ISD::CondCode Cond) { in getCondCode() function in SelectionDAG
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| /external/llvm/include/llvm/CodeGen/ |
| D | SelectionDAG.h | 565 SDValue getCondCode(ISD::CondCode Cond);
735 return getNode(ISD::SETCC, DL, VT, LHS, RHS, getCondCode(Cond));
756 LHS, RHS, True, False, getCondCode(Cond));
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| /external/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 352 AArch64CC::CondCode getCondCode() const { in getCondCode() function in __anon26fd99540211::AArch64Operand
1293 Inst.addOperand(MCOperand::createImm(getCondCode())); in addCondCodeOperands()
1814 OS << "<condcode " << getCondCode() << ">"; in print()
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| /external/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 583 ARMCC::CondCodes getCondCode() const { in getCondCode() function in __anonef5d38c20311::ARMOperand
1685 Inst.addOperand(MCOperand::createImm(unsigned(getCondCode()))); in addCondCodeOperands()
1686 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR; in addCondCodeOperands()
1712 Inst.addOperand(MCOperand::createImm(unsigned(getCondCode()))); in addITCondCodeOperands()
2767 OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">"; in print()
4658 unsigned Cond = static_cast<ARMOperand &>(*Operands[CondOp]).getCondCode(); in cvtThumbBranches()
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