Searched refs:getDefRegState (Results 1 – 17 of 17) sorted by relevance
| /external/llvm/lib/Target/ARM/ |
| D | Thumb1InstrInfo.cpp | 66 .addReg(DestReg, getDefRegState(true)); in copyPhysReg()
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| D | ARMLoadStoreOptimizer.cpp | 751 MIB.addReg(Base, getDefRegState(true)) in CreateLoadStoreMulti()
768 MIB.addReg(R.first, getDefRegState(isDef) | getKillRegState(R.second)); in CreateLoadStoreMulti()
1203 .addReg(Base, getDefRegState(true)) // WB base register in MergeBaseUpdateLSMultiple()
1327 .addReg(Base, getDefRegState(true)) // WB base register in MergeBaseUpdateLoadStore()
1330 .addReg(MO.getReg(), (isLd ? getDefRegState(true) : in MergeBaseUpdateLoadStore()
1501 .addReg(Reg, getDefRegState(true) | getDeadRegState(RegDeadKill)) in InsertLDR_STR()
1564 .addReg(EvenReg, getDefRegState(isLd) | getDeadRegState(EvenDeadKill)) in FixInvalidRegPairOp()
1565 .addReg(OddReg, getDefRegState(isLd) | getDeadRegState(OddDeadKill)); in FixInvalidRegPairOp()
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| D | ThumbRegisterInfo.cpp | 77 .addReg(DestReg, getDefRegState(true), SubIdx) in emitThumb1LoadConstPool()
96 .addReg(DestReg, getDefRegState(true), SubIdx) in emitThumb2LoadConstPool()
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| D | MLxExpansionPass.cpp | 301 .addReg(DstReg, getDefRegState(true) | getDeadRegState(DstDead)); in ExpandFPMLxInstruction()
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| D | ARMBaseInstrInfo.h | 407 return MIB.addReg(ARM::CPSR, getDefRegState(true) | getDeadRegState(isDead));
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| D | ARMBaseRegisterInfo.cpp | 395 .addReg(DestReg, getDefRegState(true), SubIdx) in emitLoadConstPool()
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| D | Thumb1FrameLowering.cpp | 648 MIB.addReg(Reg, getDefRegState(true)); in restoreCalleeSavedRegisters()
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| D | ARMFrameLowering.cpp | 1028 MIB.addReg(Regs[i], getDefRegState(true)); in emitPopInst()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIRegisterInfo.cpp | 244 .addReg(SubReg, getDefRegState(IsLoad)) in buildScratchLoadStore()
251 .addReg(Value, RegState::Implicit | getDefRegState(IsLoad)) in buildScratchLoadStore()
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| /external/llvm/lib/CodeGen/ |
| D | MachineInstrBundle.cpp | 203 MIB.addReg(Reg, getDefRegState(true) | getDeadRegState(isDead) | in finalizeBundle()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64FrameLowering.cpp | 862 MIB.addReg(Reg2, getDefRegState(true)) in restoreCalleeSavedRegisters()
863 .addReg(Reg1, getDefRegState(true)) in restoreCalleeSavedRegisters()
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| D | AArch64InstrInfo.cpp | 2019 .addReg(DestReg, getDefRegState(true)) in loadRegFromStackSlot()
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| /external/llvm/include/llvm/CodeGen/ |
| D | MachineInstrBuilder.h | 388 inline unsigned getDefRegState(bool B) { in getDefRegState() function
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | InstrEmitter.cpp | 366 MIB.addReg(VReg, getDefRegState(isOptDef) | getKillRegState(isKill) | in AddRegisterOperand()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonSplitDouble.cpp | 114 return getDefRegState(R.isDef()) | in getRegState()
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| /external/llvm/lib/Target/X86/ |
| D | X86FrameLowering.cpp | 295 .addReg(Reg, getDefRegState(!isSub) | getUndefRegState(isSub)); in emitSPUpdate()
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| D | X86InstrInfo.cpp | 6231 getDefRegState(MO.isDef()) | in unfoldMemoryOperand()
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