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Searched refs:getLocReg (Results 1 – 20 of 20) sorted by relevance

/external/llvm/lib/Target/BPF/
DBPFISelLowering.cpp220 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerFormalArguments()
333 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall()
417 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVals[i], Flag); in LowerReturn()
422 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
455 Chain = DAG.getCopyFromReg(Chain, DL, Val.getLocReg(), in LowerCallResult()
/external/llvm/lib/Target/Sparc/
DSparcISelLowering.cpp248 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Part0, Flag); in LowerReturn_32()
250 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn_32()
252 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Part1, in LowerReturn_32()
255 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Arg, Flag); in LowerReturn_32()
259 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn_32()
342 if (i+1 < RVLocs.size() && RVLocs[i+1].getLocReg() == VA.getLocReg()) { in LowerReturn_64()
350 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVal, Flag); in LowerReturn_64()
354 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn_64()
427 MF.getRegInfo().addLiveIn(VA.getLocReg(), VRegHi); in LowerFormalArguments_32()
442 unsigned loReg = MF.addLiveIn(NextVA.getLocReg(), in LowerFormalArguments_32()
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/external/llvm/lib/Target/ARM/
DARMFastISel.cpp1984 TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(Arg); in ProcessCallArgs()
1985 RegArgs.push_back(VA.getLocReg()); in ProcessCallArgs()
1997 TII.get(ARM::VMOVRRD), VA.getLocReg()) in ProcessCallArgs()
1998 .addReg(NextVA.getLocReg(), RegState::Define) in ProcessCallArgs()
2000 RegArgs.push_back(VA.getLocReg()); in ProcessCallArgs()
2001 RegArgs.push_back(NextVA.getLocReg()); in ProcessCallArgs()
2047 .addReg(RVLocs[0].getLocReg()) in FinishCall()
2048 .addReg(RVLocs[1].getLocReg())); in FinishCall()
2050 UsedRegs.push_back(RVLocs[0].getLocReg()); in FinishCall()
2051 UsedRegs.push_back(RVLocs[1].getLocReg()); in FinishCall()
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DARMISelLowering.cpp1454 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, in LowerCallResult()
1459 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, in LowerCallResult()
1473 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag); in LowerCallResult()
1477 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag); in LowerCallResult()
1487 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(), in LowerCallResult()
1535 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd.getValue(id))); in PassF64ArgInRegs()
1538 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1-id))); in PassF64ArgInRegs()
1683 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall()
2145 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg()) in IsEligibleForTailCallOptimization()
2312 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), in LowerReturn()
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/external/llvm/lib/Target/MSP430/
DMSP430ISelLowering.cpp464 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerCCCArguments()
549 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), in LowerReturn()
555 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
624 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCCCCallTo()
727 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(), in LowerCallResult()
/external/llvm/lib/Target/Mips/
DMipsFastISel.cpp1162 TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(ArgReg); in processCallArgs()
1163 CLI.OutRegs.push_back(VA.getLocReg()); in processCallArgs()
1230 ResultReg).addReg(RVLocs[0].getLocReg()); in finishCall()
1231 CLI.InRegs.push_back(RVLocs[0].getLocReg()); in finishCall()
1469 unsigned DestReg = VA.getLocReg(); in selectRet()
1504 RetRegs.push_back(VA.getLocReg()); in selectRet()
DMipsISelLowering.cpp2681 unsigned LocRegLo = VA.getLocReg(); in LowerCall()
2723 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall()
2834 SDValue Val = DAG.getCopyFromReg(Chain, DL, RVLocs[i].getLocReg(), in LowerCallResult()
3004 unsigned ArgReg = VA.getLocReg(); in LowerFormalArguments()
3193 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Flag); in LowerReturn()
3197 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
/external/llvm/lib/Target/Hexagon/
DHexagonISelLowering.cpp580 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag); in LowerReturn()
584 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
632 RVLocs[i].getLocReg(), in LowerCallResult()
772 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall()
1073 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerFormalArguments()
1078 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerFormalArguments()
1086 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerFormalArguments()
1093 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerFormalArguments()
1101 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerFormalArguments()
1108 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerFormalArguments()
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/external/llvm/lib/CodeGen/
DCallingConvLower.cpp222 Regs.push_back(MCPhysReg(Locs[I].getLocReg())); in getRemainingRegParmsForType()
/external/llvm/lib/Target/X86/
DX86FastISel.cpp1060 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) in X86SelectRet()
1089 unsigned DstReg = VA.getLocReg(); in X86SelectRet()
1098 RetRegs.push_back(VA.getLocReg()); in X86SelectRet()
3020 TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(ArgReg); in fastLowerCall()
3021 OutRegs.push_back(VA.getLocReg()); in fastLowerCall()
3184 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) && in fastLowerCall()
3192 TII.get(TargetOpcode::COPY), CopyReg).addReg(VA.getLocReg()); in fastLowerCall()
3193 InRegs.push_back(VA.getLocReg()); in fastLowerCall()
DX86ISelLowering.cpp2239 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) && in LowerReturn()
2252 if (VA.getLocReg() == X86::FP0 || in LowerReturn()
2253 VA.getLocReg() == X86::FP1) { in LowerReturn()
2267 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) { in LowerReturn()
2279 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag); in LowerReturn()
2281 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
2404 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) && in LowerCallResult()
2410 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), in LowerCallResult()
2733 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); in LowerFormalArguments()
3230 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall()
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/external/llvm/include/llvm/CodeGen/
DCallingConvLower.h148 unsigned getLocReg() const { assert(isRegLoc()); return Loc; } in getLocReg() function
/external/llvm/lib/Target/XCore/
DXCoreISelLowering.cpp1084 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getValVT(), in LowerCallResult()
1182 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCCCCallTo()
1342 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerCCCArguments()
1532 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag); in LowerReturn()
1537 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
/external/llvm/lib/Target/PowerPC/
DPPCFastISel.cpp1408 unsigned SourcePhysReg = VA.getLocReg(); in finishCall()
1615 unsigned RetReg = VA.getLocReg(); in SelectRet()
1639 RetRegs.push_back(VA.getLocReg()); in SelectRet()
DPPCISelLowering.cpp2893 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); in LowerFormalArguments_32SVR4()
4329 VA.getLocReg(), VA.getLocVT(), InFlag); in LowerCallResult()
4668 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall_32SVR4()
5812 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag); in LowerReturn()
5814 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
/external/llvm/lib/Target/AArch64/
DAArch64FastISel.cpp2957 TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(ArgReg); in processCallArgs()
2958 CLI.OutRegs.push_back(VA.getLocReg()); in processCallArgs()
3022 .addReg(RVLocs[0].getLocReg()); in finishCall()
3023 CLI.InRegs.push_back(RVLocs[0].getLocReg()); in finishCall()
3688 unsigned DestReg = VA.getLocReg(); in selectRet()
3726 RetRegs.push_back(VA.getLocReg()); in selectRet()
DAArch64ISelLowering.cpp2453 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); in LowerFormalArguments()
2669 DAG.getCopyFromReg(Chain, DL, VA.getLocReg(), VA.getLocVT(), InFlag); in LowerCallResult()
2783 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg()) in isEligibleForTailCallOptimization()
3034 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall()
3270 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Arg, Flag); in LowerReturn()
3272 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
/external/llvm/lib/Target/SystemZ/
DSystemZISelLowering.cpp921 MRI.addLiveIn(VA.getLocReg(), VReg); in LowerFormalArguments()
999 unsigned Reg = VA.getLocReg(); in canUseSiblingCall()
1068 RegsToPass.push_back(std::make_pair(VA.getLocReg(), ArgValue)); in LowerCall()
1161 SDValue RetValue = DAG.getCopyFromReg(Chain, DL, VA.getLocReg(), in LowerCall()
1224 unsigned Reg = VA.getLocReg(); in LowerReturn()
/external/llvm/lib/Target/AMDGPU/
DSIISelLowering.cpp716 unsigned Reg = VA.getLocReg(); in LowerFormalArguments()
742 Reg = ArgLocs[ArgIdx++].getLocReg(); in LowerFormalArguments()
DR600ISelLowering.cpp1668 unsigned Reg = MF.addLiveIn(VA.getLocReg(), &AMDGPU::R600_Reg128RegClass); in LowerFormalArguments()