| /external/llvm/lib/Target/X86/InstPrinter/ |
| D | X86InstComments.cpp | 40 unsigned OpReg = MI->getOperand(OperandIndex).getReg(); in getRegOperandVectorVT()
221 Src2Name = getRegName(MI->getOperand(2).getReg()); in EmitAnyX86InstComments()
230 Src1Name = getRegName(MI->getOperand(1).getReg()); in EmitAnyX86InstComments()
231 DestName = getRegName(MI->getOperand(0).getReg()); in EmitAnyX86InstComments()
237 Src2Name = getRegName(MI->getOperand(2).getReg()); in EmitAnyX86InstComments()
246 Src1Name = getRegName(MI->getOperand(1).getReg()); in EmitAnyX86InstComments()
247 DestName = getRegName(MI->getOperand(0).getReg()); in EmitAnyX86InstComments()
253 Src2Name = getRegName(MI->getOperand(2).getReg()); in EmitAnyX86InstComments()
262 Src1Name = getRegName(MI->getOperand(1).getReg()); in EmitAnyX86InstComments()
263 DestName = getRegName(MI->getOperand(0).getReg()); in EmitAnyX86InstComments()
[all …]
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZAsmPrinter.cpp | 34 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg())) in lowerRILow()
38 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg())) in lowerRILow()
39 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(1).getReg())) in lowerRILow()
48 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg())) in lowerRIHigh()
52 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg())) in lowerRIHigh()
53 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(1).getReg())) in lowerRIHigh()
61 .addReg(MI->getOperand(0).getReg()) in lowerRIEfLow()
62 .addReg(MI->getOperand(1).getReg()) in lowerRIEfLow()
63 .addReg(SystemZMC::getRegAsGR64(MI->getOperand(2).getReg())) in lowerRIEfLow()
87 .addReg(SystemZMC::getRegAsVR128(MI->getOperand(0).getReg())) in lowerSubvectorLoad()
[all …]
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCVSXCopy.cpp | 102 if ( IsVSReg(DstMO.getReg(), MRI) && in processBlock()
103 !IsVSReg(SrcMO.getReg(), MRI)) { in processBlock()
108 IsVRReg(SrcMO.getReg(), MRI) ? &PPC::VSHRCRegClass : in processBlock()
110 assert((IsF8Reg(SrcMO.getReg(), MRI) || in processBlock()
111 IsVRReg(SrcMO.getReg(), MRI) || in processBlock()
112 IsVSSReg(SrcMO.getReg(), MRI) || in processBlock()
113 IsVSFReg(SrcMO.getReg(), MRI)) && in processBlock()
122 .addImm(IsVRReg(SrcMO.getReg(), MRI) ? PPC::sub_128 : in processBlock()
127 } else if (!IsVSReg(DstMO.getReg(), MRI) && in processBlock()
128 IsVSReg(SrcMO.getReg(), MRI)) { in processBlock()
[all …]
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| D | PPCMIPeephole.cpp | 119 unsigned TrueReg1 = lookThruCopyLike(MI.getOperand(1).getReg()); in simplifyCode()
120 unsigned TrueReg2 = lookThruCopyLike(MI.getOperand(2).getReg()); in simplifyCode()
131 = lookThruCopyLike(DefMI->getOperand(1).getReg()); in simplifyCode()
133 = lookThruCopyLike(DefMI->getOperand(2).getReg()); in simplifyCode()
141 TII->get(PPC::COPY), MI.getOperand(0).getReg()) in simplifyCode()
154 MI.getOperand(1).setReg(DefMI->getOperand(1).getReg()); in simplifyCode()
155 MI.getOperand(2).setReg(DefMI->getOperand(2).getReg()); in simplifyCode()
166 TII->get(PPC::COPY), MI.getOperand(0).getReg()) in simplifyCode()
207 CopySrcReg = MI->getOperand(1).getReg(); in lookThruCopyLike()
210 CopySrcReg = MI->getOperand(2).getReg(); in lookThruCopyLike()
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| /external/llvm/lib/Target/ARM/InstPrinter/ |
| D | ARMInstPrinter.cpp | 125 printRegName(O, Dst.getReg()); in printInst()
127 printRegName(O, MO1.getReg()); in printInst()
130 printRegName(O, MO2.getReg()); in printInst()
147 printRegName(O, Dst.getReg()); in printInst()
149 printRegName(O, MO1.getReg()); in printInst()
165 if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) { in printInst()
179 if (MI->getOperand(2).getReg() == ARM::SP && in printInst()
184 printRegName(O, MI->getOperand(1).getReg()); in printInst()
194 if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) { in printInst()
208 if (MI->getOperand(2).getReg() == ARM::SP && in printInst()
[all …]
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| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| D | HexagonMCDuplexInfo.cpp | 192 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
193 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
210 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
211 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
231 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
232 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
241 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
242 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
251 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
252 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
[all …]
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| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| D | X86MCCodeEmitter.cpp | 64 if (is16BitMode(STI) && BaseReg.getReg() == 0 && in Is16BitMemOperand()
67 if ((BaseReg.getReg() != 0 && in Is16BitMemOperand()
68 X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg.getReg())) || in Is16BitMemOperand()
69 (IndexReg.getReg() != 0 && in Is16BitMemOperand()
70 X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg.getReg()))) in Is16BitMemOperand()
76 return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg()) & 0x7; in GetX86RegNum()
90 unsigned SrcReg = MI.getOperand(OpNum).getReg(); in getVEXRegisterEncoding()
102 assert(X86::K0 != MI.getOperand(OpNum).getReg() && in getWriteMaskRegisterEncoding()
229 if ((BaseReg.getReg() != 0 && in Is32BitMemOperand()
230 X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg.getReg())) || in Is32BitMemOperand()
[all …]
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| /external/dexmaker/src/dx/java/com/android/dx/dex/code/form/ |
| D | Form23x.java | 71 unsignedFitsInByte(regs.get(0).getReg()) && in isCompatible()
72 unsignedFitsInByte(regs.get(1).getReg()) && in isCompatible()
73 unsignedFitsInByte(regs.get(2).getReg()); in isCompatible()
82 bits.set(0, unsignedFitsInByte(regs.get(0).getReg())); in compatibleRegs()
83 bits.set(1, unsignedFitsInByte(regs.get(1).getReg())); in compatibleRegs()
84 bits.set(2, unsignedFitsInByte(regs.get(2).getReg())); in compatibleRegs()
93 opcodeUnit(insn, regs.get(0).getReg()), in writeTo()
94 codeUnit(regs.get(1).getReg(), regs.get(2).getReg())); in writeTo()
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| D | Form33x.java | 75 unsignedFitsInByte(regs.get(0).getReg()) && in isCompatible()
76 unsignedFitsInByte(regs.get(1).getReg()) && in isCompatible()
77 unsignedFitsInShort(regs.get(2).getReg()); in isCompatible()
86 bits.set(0, unsignedFitsInByte(regs.get(0).getReg())); in compatibleRegs()
87 bits.set(1, unsignedFitsInByte(regs.get(1).getReg())); in compatibleRegs()
88 bits.set(2, unsignedFitsInShort(regs.get(2).getReg())); in compatibleRegs()
98 codeUnit(regs.get(0).getReg(), regs.get(1).getReg()), in writeTo()
99 (short) regs.get(2).getReg()); in writeTo()
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| D | Form12x.java | 97 if (rs1.getReg() != regs.get(0).getReg()) { in isCompatible()
107 return unsignedFitsInNibble(rs1.getReg()) && in isCompatible()
108 unsignedFitsInNibble(rs2.getReg()); in isCompatible()
117 bits.set(0, unsignedFitsInNibble(regs.get(0).getReg())); in compatibleRegs()
118 bits.set(1, unsignedFitsInNibble(regs.get(1).getReg())); in compatibleRegs()
135 makeByte(regs.get(sz - 2).getReg(), in writeTo()
136 regs.get(sz - 1).getReg()))); in writeTo()
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| D | Form41c.java | 95 if (reg.getReg() != regs.get(1).getReg()) { in isCompatible()
105 if (!unsignedFitsInShort(reg.getReg())) { in isCompatible()
122 boolean compat = unsignedFitsInByte(regs.get(0).getReg()); in compatibleRegs()
127 if (regs.get(0).getReg() == regs.get(1).getReg()) { in compatibleRegs()
142 write(out, opcodeUnit(insn), cpi, (short) regs.get(0).getReg()); in writeTo()
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| D | Form32x.java | 69 unsignedFitsInShort(regs.get(0).getReg()) && in isCompatible()
70 unsignedFitsInShort(regs.get(1).getReg()); in isCompatible()
79 bits.set(0, unsignedFitsInShort(regs.get(0).getReg())); in compatibleRegs()
80 bits.set(1, unsignedFitsInShort(regs.get(1).getReg())); in compatibleRegs()
91 (short) regs.get(0).getReg(), in writeTo()
92 (short) regs.get(1).getReg()); in writeTo()
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| D | Form22x.java | 70 unsignedFitsInByte(regs.get(0).getReg()) && in isCompatible()
71 unsignedFitsInShort(regs.get(1).getReg()); in isCompatible()
80 bits.set(0, unsignedFitsInByte(regs.get(0).getReg())); in compatibleRegs()
81 bits.set(1, unsignedFitsInShort(regs.get(1).getReg())); in compatibleRegs()
90 opcodeUnit(insn, regs.get(0).getReg()), in writeTo()
91 (short) regs.get(1).getReg()); in writeTo()
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| D | Form31c.java | 92 if (reg.getReg() != regs.get(1).getReg()) { in isCompatible()
102 if (!unsignedFitsInByte(reg.getReg())) { in isCompatible()
120 boolean compat = unsignedFitsInByte(regs.get(0).getReg()); in compatibleRegs()
125 if (regs.get(0).getReg() == regs.get(1).getReg()) { in compatibleRegs()
140 write(out, opcodeUnit(insn, regs.get(0).getReg()), cpi); in writeTo()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonSplitDouble.cpp | 203 unsigned R = Op.getReg(); in isFixedInstr()
252 unsigned T = MO.getReg(); in partitionRegisters()
410 if (Op.isReg() && Part.count(Op.getReg())) in isProfitable()
469 unsigned PR = Cond[1].getReg(); in collectIndRegsForLoop()
477 CmpI = MRI->getVRegDef(CmpI->getOperand(1).getReg()); in collectIndRegsForLoop()
504 unsigned R = MD.getReg(); in collectIndRegsForLoop()
520 unsigned T = UseI->getOperand(0).getReg(); in collectIndRegsForLoop()
573 unsigned R = Op.getReg(); in createHalfInstr()
614 UUPairMap::const_iterator F = PairMap.find(ValOp.getReg()); in splitMemRef()
621 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg()) in splitMemRef()
[all …]
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| D | HexagonPeephole.cpp | 141 unsigned DstReg = Dst.getReg(); in runOnMachineFunction()
142 unsigned SrcReg = Src.getReg(); in runOnMachineFunction()
163 unsigned DstReg = Dst.getReg(); in runOnMachineFunction()
164 unsigned SrcReg = Src2.getReg(); in runOnMachineFunction()
180 unsigned DstReg = Dst.getReg(); in runOnMachineFunction()
181 unsigned SrcReg = Src1.getReg(); in runOnMachineFunction()
192 unsigned DstReg = Dst.getReg(); in runOnMachineFunction()
193 unsigned SrcReg = Src.getReg(); in runOnMachineFunction()
215 unsigned DstReg = Dst.getReg(); in runOnMachineFunction()
216 unsigned SrcReg = Src.getReg(); in runOnMachineFunction()
[all …]
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| D | HexagonVLIWPacketizer.cpp | 117 unsigned R = MO.getReg(); in hasWriteToReadDep()
283 if (MO.isReg() && MO.isUse() && (MO.getReg() == DepReg)) in isCallDependent()
351 if (MO.isReg() && MO.getReg() == MI->getOperand(0).getReg()) in cleanUpDotCur()
388 unsigned DestReg = MI->getOperand(0).getReg(); in canPromoteToDotCur()
391 if (MO.isReg() && MO.getReg() == DestReg) in canPromoteToDotCur()
458 DefRegsSet.insert(MO.getReg()); in getPostIncrementOperand()
461 if (MO.isReg() && MO.isUse() && DefRegsSet.count(MO.getReg())) in getPostIncrementOperand()
532 if (Val.isReg() && Val.getReg() != DepReg) in canPromoteToNewValueStore()
554 getPostIncrementOperand(MI, HII).getReg() == DepReg) { in canPromoteToNewValueStore()
559 getPostIncrementOperand(PacketMI, HII).getReg() == DepReg) { in canPromoteToNewValueStore()
[all …]
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIFixSGPRCopies.cpp | 119 !TargetRegisterInfo::isVirtualRegister(MI.getOperand(i).getReg())) in hasVGPROperands()
122 if (TRI->hasVGPRs(MRI.getRegClass(MI.getOperand(i).getReg()))) in hasVGPROperands()
132 unsigned DstReg = Copy.getOperand(0).getReg(); in getCopyRegClasses()
133 unsigned SrcReg = Copy.getOperand(1).getReg(); in getCopyRegClasses()
182 unsigned DstReg = MI.getOperand(0).getReg(); in foldVGPRCopyIntoRegSequence()
214 MI.getOperand(0).setReg(CopyUse.getOperand(0).getReg()); in foldVGPRCopyIntoRegSequence()
217 unsigned SrcReg = MI.getOperand(I).getReg(); in foldVGPRCopyIntoRegSequence()
218 unsigned SrcSubReg = MI.getOperand(I).getReg(); in foldVGPRCopyIntoRegSequence()
262 if (!TargetRegisterInfo::isVirtualRegister(MI.getOperand(0).getReg())) in runOnMachineFunction()
276 unsigned Reg = MI.getOperand(0).getReg(); in runOnMachineFunction()
[all …]
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| D | R600ExpandSpecialInstrs.cpp | 87 DstOp.getReg(), AMDGPU::OQAP); in runOnMachineFunction()
95 MI.getOperand(LDSPredSelIdx).getReg()); in runOnMachineFunction()
107 MI.getOperand(0).getReg(), // dst in runOnMachineFunction()
108 MI.getOperand(1).getReg(), // src0 in runOnMachineFunction()
129 DstReg = MI.getOperand(Chan).getReg(); in runOnMachineFunction()
134 DstReg, MI.getOperand(3 + (Chan % 2)).getReg(), PReg); in runOnMachineFunction()
160 DstReg = MI.getOperand(Chan-2).getReg(); in runOnMachineFunction()
163 DstReg, MI.getOperand(3 + (Chan % 2)).getReg(), PReg); in runOnMachineFunction()
183 unsigned DstReg = MI.getOperand(0).getReg(); in runOnMachineFunction()
202 unsigned DstReg = MI.getOperand(0).getReg(); in runOnMachineFunction()
[all …]
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| D | SILowerI1Copies.cpp | 90 unsigned Reg = MI.getOperand(0).getReg(); in runOnMachineFunction()
103 if (!TargetRegisterInfo::isVirtualRegister(Src.getReg()) || in runOnMachineFunction()
104 !TargetRegisterInfo::isVirtualRegister(Dst.getReg())) in runOnMachineFunction()
107 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst.getReg()); in runOnMachineFunction()
108 const TargetRegisterClass *SrcRC = MRI.getRegClass(Src.getReg()); in runOnMachineFunction()
112 I1Defs.push_back(Dst.getReg()); in runOnMachineFunction()
115 MachineInstr *DefInst = MRI.getUniqueVRegDef(Src.getReg()); in runOnMachineFunction()
118 I1Defs.push_back(Dst.getReg()); in runOnMachineFunction()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64AdvSIMDScalarPass.cpp | 142 return MI->getOperand(1).getReg(); in getSrcFromCopy()
147 return MI->getOperand(1).getReg(); in getSrcFromCopy()
152 if (isFPR64(MI->getOperand(0).getReg(), MI->getOperand(0).getSubReg(), in getSrcFromCopy()
154 isGPR64(MI->getOperand(1).getReg(), MI->getOperand(1).getSubReg(), MRI)) in getSrcFromCopy()
155 return MI->getOperand(1).getReg(); in getSrcFromCopy()
156 if (isGPR64(MI->getOperand(0).getReg(), MI->getOperand(0).getSubReg(), in getSrcFromCopy()
158 isFPR64(MI->getOperand(1).getReg(), MI->getOperand(1).getSubReg(), in getSrcFromCopy()
161 return MI->getOperand(1).getReg(); in getSrcFromCopy()
212 unsigned OrigSrc0 = MI->getOperand(1).getReg(); in isProfitableToTransform()
213 unsigned OrigSrc1 = MI->getOperand(2).getReg(); in isProfitableToTransform()
[all …]
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| /external/llvm/lib/Target/Mips/Disassembler/ |
| D | MipsDisassembler.cpp | 498 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) { in getReg() function
579 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeAddiGroupBranch()
582 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeAddiGroupBranch()
618 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeDaddiGroupBranch()
621 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeDaddiGroupBranch()
660 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeBlezlGroupBranch()
663 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeBlezlGroupBranch()
704 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeBgtzlGroupBranch()
707 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeBgtzlGroupBranch()
752 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeBgtzGroupBranch()
[all …]
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| /external/llvm/lib/Target/ARM/ |
| D | A15SDOptimizer.cpp | 142 unsigned Reg = MO.getReg(); in usesRegClass()
172 SReg = MI->getOperand(1).getReg(); in getPrefSPRLane()
201 unsigned Reg = MO.getReg(); in eraseInstrWithNoUses()
224 unsigned DefReg = MODef.getReg(); in eraseInstrWithNoUses()
254 return optimizeAllLanesPattern(MI, MI->getOperand(1).getReg()); in optimizeSDPattern()
258 unsigned DPRReg = MI->getOperand(1).getReg(); in optimizeSDPattern()
259 unsigned SPRReg = MI->getOperand(2).getReg(); in optimizeSDPattern()
262 MachineInstr *DPRMI = MRI->getVRegDef(MI->getOperand(1).getReg()); in optimizeSDPattern()
263 MachineInstr *SPRMI = MRI->getVRegDef(MI->getOperand(2).getReg()); in optimizeSDPattern()
280 unsigned FullReg = SPRMI->getOperand(1).getReg(); in optimizeSDPattern()
[all …]
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| /external/llvm/lib/CodeGen/ |
| D | TwoAddressInstructionPass.cpp | 204 unsigned MOReg = MO.getReg(); in sink3AddrInstruction()
208 UseRegs.insert(MO.getReg()); in sink3AddrInstruction()
217 DefReg = MO.getReg(); in sink3AddrInstruction()
274 unsigned MOReg = MO.getReg(); in sink3AddrInstruction()
344 TmpReg = Def->getOperand(1).getReg(); in isRevCopyChain()
385 DstReg = MI.getOperand(0).getReg(); in isCopyToReg()
386 SrcReg = MI.getOperand(1).getReg(); in isCopyToReg()
388 DstReg = MI.getOperand(0).getReg(); in isCopyToReg()
389 SrcReg = MI.getOperand(2).getReg(); in isCopyToReg()
478 if (!MO.isReg() || !MO.isUse() || MO.getReg() != Reg) in isTwoAddrUse()
[all …]
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| /external/dexmaker/src/dx/java/com/android/dx/ssa/ |
| D | DeadCodeRemover.java | 108 useList[source.getReg()].remove(insnS); in run()
112 source.getReg()))) { in run()
117 worklist.set(source.getReg()); in run()
154 useList[source.getReg()].remove(insn); in pruneDeadInstructions()
160 for (SsaInsn use : useList[result.getReg()]) { in pruneDeadInstructions()
204 || !isCircularNoSideEffect(result.getReg(), set)) { in isCircularNoSideEffect()
252 noSideEffectRegs.set(insn.getResult().getReg()); in visitMoveInsn()
260 noSideEffectRegs.set(phi.getResult().getReg()); in visitPhiInsn()
268 noSideEffectRegs.set(result.getReg()); in visitNonMoveInsn()
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