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Searched refs:getSchedulingPreference (Results 1 – 7 of 7) sorted by relevance

/external/llvm/lib/CodeGen/SelectionDAG/
DSelectionDAGISel.cpp308 TLI->getSchedulingPreference() == Sched::Source) in createDefaultScheduler()
310 if (TLI->getSchedulingPreference() == Sched::RegPressure) in createDefaultScheduler()
312 if (TLI->getSchedulingPreference() == Sched::Hybrid) in createDefaultScheduler()
314 if (TLI->getSchedulingPreference() == Sched::VLIW) in createDefaultScheduler()
316 assert(TLI->getSchedulingPreference() == Sched::ILP && in createDefaultScheduler()
DScheduleDAGSDNodes.cpp85 SU->SchedulingPref = TLI.getSchedulingPreference(N); in newSUnit()
/external/llvm/lib/Target/ARM/
DARMISelLowering.h399 Sched::Preference getSchedulingPreference(SDNode *N) const override;
DARMISelLowering.cpp1277 Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const { in getSchedulingPreference() function in ARMTargetLowering
/external/llvm/lib/Target/PowerPC/
DPPCISelLowering.h480 Sched::Preference getSchedulingPreference(SDNode *N) const override;
DPPCISelLowering.cpp11580 Sched::Preference PPCTargetLowering::getSchedulingPreference(SDNode *N) const { in getSchedulingPreference() function in PPCTargetLowering
11582 return TargetLowering::getSchedulingPreference(N); in getSchedulingPreference()
/external/llvm/include/llvm/Target/
DTargetLowering.h367 Sched::Preference getSchedulingPreference() const { in getSchedulingPreference() function
374 virtual Sched::Preference getSchedulingPreference(SDNode *) const { in getSchedulingPreference() function