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Searched refs:i17 (Results 1 – 25 of 43) sorted by relevance

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/external/llvm/test/Integer/
Dnewcasts_bt.ll5 define void @"NewCasts" (i17 %x) {
6 %a = zext i17 %x to i32
7 %b = sext i17 %x to i32
8 %c = trunc i17 %x to i8
9 %d = uitofp i17 %x to float
10 %e = sitofp i17 %x to double
11 %f = fptoui float %d to i17
12 %g = fptosi double %e to i17
16 %l = inttoptr i17 %x to i32*
22 define i17 @"ZExtConst" () {
[all …]
D2007-01-19-TruncSext.ll7 @ARRAY = global [ 20 x i17 ] zeroinitializer
14 %P = getelementptr [20 x i17], [20 x i17]* @ARRAY, i32 0, i32 %index
15 %Result = trunc i32 %Z to i17
16 store i17 %Result, i17* %P
23 %P = getelementptr [20 x i17], [20 x i17]* @ARRAY, i32 0, i32 0
24 %X = load i17, i17* %P
25 %result = sext i17 %X to i32
/external/llvm/test/Transforms/InstCombine/
Dapint-cast.ll6 define i17 @test1(i17 %a) {
7 %tmp = zext i17 %a to i37 ; <i37> [#uses=2]
9 ; CHECK: %tmp21 = lshr i17 %a, 8
11 ; CHECK: %tmp5 = shl i17 %a, 8
13 ; CHECK: %tmp.upgrd.32 = or i17 %tmp21, %tmp5
14 %tmp.upgrd.3 = trunc i37 %tmp.upgrd.32 to i17 ; <i17> [#uses=1]
15 ret i17 %tmp.upgrd.3
16 ; CHECK: ret i17 %tmp.upgrd.32
Dapint-and-or-and.ll17 define i17 @test1(i17 %X, i17 %Y) {
18 %A = and i17 %X, 7
19 %B = and i17 %Y, 8
20 %C = or i17 %A, %B
21 %D = and i17 %C, 7 ;; This cannot include any bits from %Y!
22 ret i17 %D
Dapint-mul1.ll8 define i17 @test1(i17 %X) {
9 %Y = mul i17 %X, 1024
10 ret i17 %Y
Dapint-shift.ll83 define i17 @test9(i17 %A) {
84 %B = shl i17 %A, 16 ; <i17> [#uses=1]
85 %C = lshr i17 %B, 16 ; <i17> [#uses=1]
86 ret i17 %C
D2007-10-31-RangeCrash.ll7 %tmp50.i17 = icmp slt i32 0, 4 ; <i1> [#uses=1]
8 br i1 %tmp50.i17, label %bb.i, label %calculateColorSpecificBlackLevel.exit
/external/llvm/test/CodeGen/X86/
D2009-07-20-DAGCombineBug.ll12 br label %bb3.i17
14 bb3.i9: ; preds = %bb3.i17
21 br label %bb3.i17
23 bb3.i17: ; preds = %bb2.i16, %entry
26 bsR.exit18: ; preds = %bb3.i17
D2011-01-07-LegalizeTypesCrash.ll7 %i17 = icmp eq <4 x i8> undef, zeroinitializer
8 %cond = extractelement <4 x i1> %i17, i32 0
11 %cond3 = extractelement <4 x i1> %i17, i32 1
14 %cond8 = extractelement <4 x i1> %i17, i32 2
D2011-05-27-CrossClassCoalescing.ll24 br i1 undef, label %for.inc.i, label %if.then.i17
26 if.then.i17: ; preds = %for.body.i
38 for.inc.i: ; preds = %if.then.i17, %for.body.i
39 %tmp351.i = phi i32 [ %add33.i, %if.then.i17 ], [ %tmp3524.i, %for.body.i ]
D2008-09-09-LinearScanBug.ll20 br i1 false, label %land_rhs3.i.i.i14, label %lor_rhs.i.i.i17
23 br i1 false, label %forcond1.backedge.i.i20, label %lor_rhs.i.i.i17
25 lor_rhs.i.i.i17: ; preds = %land_rhs3.i.i.i14, %forinc.i.i11
30 forcond1.backedge.i.i20: ; preds = %lor_rhs.i.i.i17, %land_rhs3.i.i.i14
31 …%p_87.addr.0.be.i.i18 = phi i32 [ %add.i.i.i16, %lor_rhs.i.i.i17 ], [ 0, %land_rhs3.i.i.i14 ] ; <…
Davx-load-store.ll15 %tmp1.i17 = load <8 x float>, <8 x float>* %1, align 32
17 tail call void @dummy(<4 x double> %tmp1.i, <8 x float> %tmp1.i17, <4 x i64> %tmp1.i16) nounwind
19 store <8 x float> %tmp1.i17, <8 x float>* %1, align 32
D2007-11-30-LoadFolding-Bug.ll40 …%din_addr.1.reg2mem.0.i17.i = phi double [ 0.000000e+00, %cond_next36.i ], [ %tmp16.i25.i, %bb.i28…
41 %tmp1.i18.i = fptosi double %din_addr.1.reg2mem.0.i17.i to i32 ; <i32> [#uses=2]
/external/v8/test/mjsunit/asm/embenchen/
Dzlib.js5772 … 0, i9 = 0, i10 = 0, i11 = 0, i12 = 0, i13 = 0, i14 = 0, i15 = 0, i16 = 0, i17 = 0, i18 = 0, i19 =…
5811 i17 = i4 + 56 | 0;
5855 i64 = HEAP32[i17 >> 2] | 0;
6944 HEAP32[i17 >> 2] = i64;
6951 i64 = HEAP32[i17 >> 2] | 0;
7437 HEAP32[i17 >> 2] = i64;
7460 HEAP32[i17 >> 2] = i64;
7507 …= 0, i8 = 0, i9 = 0, i10 = 0, i11 = 0, i13 = 0, i14 = 0, i15 = 0, i16 = 0, i17 = 0, i18 = 0, i19 =…
8308 i17 = i23;
8325 i17 = i22;
[all …]
Dlua_binarytrees.js7386 …= 0, i8 = 0, i9 = 0, i10 = 0, i11 = 0, i13 = 0, i14 = 0, i15 = 0, i16 = 0, i17 = 0, i18 = 0, i19 =…
8187 i17 = i23;
8204 i17 = i22;
8218 …0) ? (i17 = _sbrk(i18 | 0) | 0, i16 = _sbrk(0) | 0, (i16 | 0) != (-1 | 0) & (i17 | 0) != (-1 | 0) …
8236 if ((i17 | 0) == (i16 + i20 | 0)) {
8247 …? (HEAP32[i21 + 12 >> 2] & 8 | 0) == 0 : 0) ? i15 >>> 0 >= i16 >>> 0 & i15 >>> 0 < i17 >>> 0 : 0) {
8264 if (i17 >>> 0 < (HEAP32[12928 >> 2] | 0) >>> 0) {
8265 HEAP32[12928 >> 2] = i17;
8267 i19 = i17 + i14 | 0;
8282 HEAP32[i16 >> 2] = i17;
[all …]
Dbox2d.js6152 …= 0, i8 = 0, i9 = 0, i10 = 0, i11 = 0, i13 = 0, i14 = 0, i15 = 0, i16 = 0, i17 = 0, i18 = 0, i19 =…
6953 i17 = i23;
6970 i17 = i22;
6984 …0) ? (i17 = _sbrk(i18 | 0) | 0, i16 = _sbrk(0) | 0, (i16 | 0) != (-1 | 0) & (i17 | 0) != (-1 | 0) …
7002 if ((i17 | 0) == (i16 + i20 | 0)) {
7013 …? (HEAP32[i21 + 12 >> 2] & 8 | 0) == 0 : 0) ? i15 >>> 0 >= i16 >>> 0 & i15 >>> 0 < i17 >>> 0 : 0) {
7030 if (i17 >>> 0 < (HEAP32[7176 >> 2] | 0) >>> 0) {
7031 HEAP32[7176 >> 2] = i17;
7033 i19 = i17 + i14 | 0;
7048 HEAP32[i16 >> 2] = i17;
[all …]
Dfannkuch.js5744 …= 0, i8 = 0, i9 = 0, i10 = 0, i11 = 0, i13 = 0, i14 = 0, i15 = 0, i16 = 0, i17 = 0, i18 = 0, i19 =…
6545 i17 = i23;
6562 i17 = i22;
6576 …0) ? (i17 = _sbrk(i18 | 0) | 0, i16 = _sbrk(0) | 0, (i16 | 0) != (-1 | 0) & (i17 | 0) != (-1 | 0) …
6594 if ((i17 | 0) == (i16 + i20 | 0)) {
6605 …? (HEAP32[i21 + 12 >> 2] & 8 | 0) == 0 : 0) ? i15 >>> 0 >= i16 >>> 0 & i15 >>> 0 < i17 >>> 0 : 0) {
6622 if (i17 >>> 0 < (HEAP32[72 >> 2] | 0) >>> 0) {
6623 HEAP32[72 >> 2] = i17;
6625 i19 = i17 + i14 | 0;
6640 HEAP32[i16 >> 2] = i17;
[all …]
Dmemops.js5689 …= 0, i8 = 0, i9 = 0, i10 = 0, i11 = 0, i13 = 0, i14 = 0, i15 = 0, i16 = 0, i17 = 0, i18 = 0, i19 =…
6490 i17 = i23;
6507 i17 = i22;
6521 …0) ? (i17 = _sbrk(i18 | 0) | 0, i16 = _sbrk(0) | 0, (i16 | 0) != (-1 | 0) & (i17 | 0) != (-1 | 0) …
6539 if ((i17 | 0) == (i16 + i20 | 0)) {
6550 …? (HEAP32[i21 + 12 >> 2] & 8 | 0) == 0 : 0) ? i15 >>> 0 >= i16 >>> 0 & i15 >>> 0 < i17 >>> 0 : 0) {
6567 if (i17 >>> 0 < (HEAP32[56 >> 2] | 0) >>> 0) {
6568 HEAP32[56 >> 2] = i17;
6570 i19 = i17 + i14 | 0;
6585 HEAP32[i16 >> 2] = i17;
[all …]
Dfasta.js5920 …= 0, i8 = 0, i9 = 0, i10 = 0, i11 = 0, i13 = 0, i14 = 0, i15 = 0, i16 = 0, i17 = 0, i18 = 0, i19 =…
6721 i17 = i23;
6738 i17 = i22;
6752 …0) ? (i17 = _sbrk(i18 | 0) | 0, i16 = _sbrk(0) | 0, (i16 | 0) != (-1 | 0) & (i17 | 0) != (-1 | 0) …
6770 if ((i17 | 0) == (i16 + i20 | 0)) {
6781 …? (HEAP32[i21 + 12 >> 2] & 8 | 0) == 0 : 0) ? i15 >>> 0 >= i16 >>> 0 & i15 >>> 0 < i17 >>> 0 : 0) {
6798 if (i17 >>> 0 < (HEAP32[600 >> 2] | 0) >>> 0) {
6799 HEAP32[600 >> 2] = i17;
6801 i19 = i17 + i14 | 0;
6816 HEAP32[i16 >> 2] = i17;
[all …]
/external/llvm/test/Transforms/InstSimplify/
Dapint-or.ll28 define i17 @test3(i17 %X) {
29 %Y = or i17 %X, -1
30 ret i17 %Y
32 ; CHECK-NEXT: ret i17 -1
/external/llvm/test/Transforms/CodeGenPrepare/X86/
Dwiden_switch.ll39 %trunc = trunc i32 %a to i17
40 switch i17 %trunc, label %sw.default [
41 i17 10, label %sw.bb0
42 i17 -1, label %sw.bb1
59 ; X86: %0 = zext i17 %trunc to i32
/external/llvm/test/Transforms/CodeGenPrepare/AArch64/
Dwiden_switch.ll39 %trunc = trunc i32 %a to i17
40 switch i17 %trunc, label %sw.default [
41 i17 10, label %sw.bb0
42 i17 -1, label %sw.bb1
59 ; ARM64: %0 = zext i17 %trunc to i32
/external/llvm/test/CodeGen/ARM/
D2010-09-21-OptCmpBug.ll38 br i1 undef, label %bb3.i17, label %bb2.i16
43 bb3.i17: ; preds = %bb1.i13
46 bb4.i18: ; preds = %bb3.i17
73 bb23.i: ; preds = %bb3.i17
/external/llvm/test/DebugInfo/Generic/
D2010-05-03-OriginDIE.ll15 %data_addr.i17 = alloca i64, align 8 ; <i64*> [#uses=2]
26 …call void @llvm.dbg.declare(metadata i64* %data_addr.i17, metadata !8, metadata !DIExpression()) n…
27 store i64 %a12, i64* %data_addr.i17, align 8
31 …call void @llvm.dbg.value(metadata i64* %data_addr.i17, i64 0, metadata !34, metadata !DIExpressio…
32 %a13 = load volatile i64, i64* %data_addr.i17, align 8 ; <i64> [#uses=1]
/external/llvm/test/CodeGen/AMDGPU/
Dwrong-transalu-pos-fix.ll12 %z.i17 = tail call i32 @llvm.r600.read.global.size.z() #1
13 %mul3 = mul i32 %mul, %z.i17
26 %add = mul i32 %mul819, %z.i17

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