| /external/ltrace/sysdeps/linux-gnu/arm/ |
| D | trace.c | 444 const int imm1 = SBITS(inst1, 0, 10); in thumb_get_next_pcs() local
450 = ((imm1 << 12) + (imm2 << 1)); in thumb_get_next_pcs()
476 const unsigned imm1 = BITS(inst1, 0, 5); in thumb_get_next_pcs() local
483 offset += (imm1 << 12) + (imm2 << 1); in thumb_get_next_pcs()
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| /external/mesa3d/src/gallium/drivers/nv50/codegen/ |
| D | nv50_ir_peephole.cpp | 390 ImmediateValue &imm0, ImmediateValue &imm1) in expr() argument
392 struct Storage *const a = &imm0.reg, *const b = &imm1.reg; in expr()
559 ImmediateValue imm1; in tryCollapseChainedMULs() local
570 if (mul1->src(s1 = 0).getImmediate(imm1) || in tryCollapseChainedMULs()
571 mul1->src(s1 = 1).getImmediate(imm1)) { in tryCollapseChainedMULs()
575 mul1->setSrc(s1, bld.loadImm(NULL, f * imm1.reg.data.f32)); in tryCollapseChainedMULs()
603 if (!insn->src(s2).mod && !insn->src(t2).getImmediate(imm1)) in tryCollapseChainedMULs()
798 ImmediateValue imm1; in opnd() local
799 if (si->src(1).getImmediate(imm1)) { in opnd()
802 i->setSrc(1, bld.loadImm(NULL, imm0.reg.data.u32 + imm1.reg.data.u32)); in opnd()
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| /external/pcre/dist/sljit/ |
| D | sljitNativeARM_32.c | 1181 sljit_uw imm1; in generate_int() local
1224 imm1 = SRC2_IMM | ((imm >> 16) & 0xff) | (((rol + 4) & 0xf) << 8); in generate_int()
1228 imm1 = SRC2_IMM | ((imm >> 24) & 0xff) | ((rol & 0xf) << 8); in generate_int()
1263 imm1 = SRC2_IMM | ((imm >> 24) & 0xff) | ((rol & 0xf) << 8); in generate_int()
1283 …ush_inst(compiler, EMIT_DATA_PROCESS_INS(positive ? MOV_DP : MVN_DP, 0, reg, SLJIT_UNUSED, imm1))); in generate_int()
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| /external/vixl/test/ |
| D | test-simulator-a64.cc | 175 const VRegister& vd, int imm1, const VRegister& vn, int imm2);
2404 for (unsigned imm1 = 0; imm1 < inputs_imm1_length; imm1++) { in TestOpImmOpImmNEON() local
2414 (imm1 * inputs_imm2_length * vd_lane_count) + in TestOpImmOpImmNEON()
2436 (imm1 * inputs_imm2_length * vd_lane_count) + in TestOpImmOpImmNEON()
2440 unsigned input_index_imm1 = imm1; in TestOpImmOpImmNEON()
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| /external/llvm/lib/Target/X86/ |
| D | README-SSE.txt | 467 INSERTPS can match any insert (extract, imm1), imm2 for 4 x float, and insert
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| /external/valgrind/VEX/priv/ |
| D | host_ppc_defs.c | 3138 UInt imm1, UInt imm2, UInt opc2, in mkFormMD() argument
3145 vassert(imm1 < 0x40); in mkFormMD()
3150 ((imm1 & 0x1F)<<11) | (imm2<<5) | in mkFormMD()
3151 (opc2<<2) | ((imm1 >> 5)<<1)); in mkFormMD()
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| D | guest_arm_toIR.c | 2569 UInt imm1, UInt imm3, UInt imm8 ) in thumbExpandImm() argument
2571 vassert(imm1 < (1<<1)); in thumbExpandImm()
2574 UInt i_imm3_a = (imm1 << 4) | (imm3 << 1) | ((imm8 >> 7) & 1); in thumbExpandImm()
2606 UInt imm1 = SLICE_UInt(i0,10,10); in thumbExpandImm_from_I0_I1() local
2609 return thumbExpandImm(updatesC, imm1, imm3, imm8); in thumbExpandImm_from_I0_I1()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsFastISel.cpp | 174 unsigned Op0, bool Op0IsKill, uint64_t imm1, in fastEmitInst_riir() argument
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| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 4295 // SETPAN #imm1
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| D | ARMInstrInfo.td | 4313 // SETPAN #imm1
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| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXIntrinsics.td | 911 def imm1 : NVPTXInst<(outs regclass:$dst),
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrFormats.td | 635 // {0} - imm1: #8 or #16
|