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Searched refs:insertq (Results 1 – 8 of 8) sorted by relevance

/external/llvm/test/MC/X86/
Dx86_64-sse4a.s11 insertq $6, $5, %xmm1, %xmm0 label
12 # CHECK: insertq $6, $5, %xmm1, %xmm0
15 insertq %xmm1, %xmm0 label
16 # CHECK: insertq %xmm1, %xmm0
/external/llvm/test/CodeGen/X86/
Dsse4a-intrinsics-fast-isel.ll41 ; X32-NEXT: insertq $6, $5, %xmm1, %xmm0
46 ; X64-NEXT: insertq $6, $5, %xmm1, %xmm0
56 ; X32-NEXT: insertq %xmm1, %xmm0
61 ; X64-NEXT: insertq %xmm1, %xmm0
63 %res = call <2 x i64> @llvm.x86.sse4a.insertq(<2 x i64> %x, <2 x i64> %y)
66 declare <2 x i64> @llvm.x86.sse4a.insertq(<2 x i64>, <2 x i64>) nounwind readnone
Dsse4a.ll43 ; CHECK: insertq
52 ; CHECK: insertq
53 %1 = tail call <2 x i64> @llvm.x86.sse4a.insertq(<2 x i64> %x, <2 x i64> %y) nounwind
57 declare <2 x i64> @llvm.x86.sse4a.insertq(<2 x i64>, <2 x i64>) nounwind
Dvector-shuffle-sse4a.ll194 ; ALL-NEXT: insertq {{.*#+}} xmm0 = xmm1[0,1,2,3,4,5,6,7],xmm0[u,u,u,u,u,u,u,u]
203 ; ALL-NEXT: insertq {{.*#+}} xmm0 = xmm0[0,1],xmm1[0],xmm0[3,4,5,6,7,u,u,u,u,u,u,u,u]
213 ; ALL-NEXT: insertq {{.*#+}} xmm0 = xmm0[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u]
222 ; ALL-NEXT: insertq {{.*#+}} xmm0 = xmm0[0,0,2,3,4,5,6,7,u,u,u,u,u,u,u,u]
231 ; ALL-NEXT: insertq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3,4,5,6,7,u,u,u,u,u,u,u,u]
240 ; ALL-NEXT: insertq {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3,4,5,6,7,u,u,u,u,u,u,u,u]
249 ; ALL-NEXT: insertq {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,1],xmm0[4,5,6,7,u,u,u,u,u,u,u,u]
258 ; ALL-NEXT: insertq {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[0,1],xmm0[6,7,u,u,u,u,u,u,u,u]
267 ; ALL-NEXT: insertq {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5],xmm1[0,1],xmm0[u,u,u,u,u,u,u,u]
276 ; ALL-NEXT: insertq {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,1,2,3],xmm0[6,7,u,u,u,u,u,u,u,u]
[all …]
/external/llvm/test/Transforms/InstCombine/
Dx86-sse4a.ll117 ; CHECK-NEXT: %1 = tail call <2 x i64> @llvm.x86.sse4a.insertq(<2 x i64> %x, <2 x i64> %y)
119 %1 = tail call <2 x i64> @llvm.x86.sse4a.insertq(<2 x i64> %x, <2 x i64> %y) nounwind
127 …%1 = tail call <2 x i64> @llvm.x86.sse4a.insertq(<2 x i64> %x, <2 x i64> <i64 8, i64 658>) nounwind
134 …%1 = tail call <2 x i64> @llvm.x86.sse4a.insertq(<2 x i64> <i64 0, i64 0>, <2 x i64> <i64 8, i64 6…
141 …%1 = tail call <2 x i64> @llvm.x86.sse4a.insertq(<2 x i64> <i64 1, i64 undef>, <2 x i64> <i64 8, i…
275 ; CHECK-NEXT: %1 = tail call <2 x i64> @llvm.x86.sse4a.insertq(<2 x i64> %x, <2 x i64> %y)
278 %2 = tail call <2 x i64> @llvm.x86.sse4a.insertq(<2 x i64> %1, <2 x i64> %y) nounwind
285 %1 = tail call <2 x i64> @llvm.x86.sse4a.insertq(<2 x i64> %x, <2 x i64> %y) nounwind
332 ; CHECK: declare <2 x i64> @llvm.x86.sse4a.insertq
333 declare <2 x i64> @llvm.x86.sse4a.insertq(<2 x i64>, <2 x i64>) nounwind
/external/llvm/test/MC/Disassembler/X86/
Dx86-64.txt71 # CHECK: insertq $6, $5, %xmm1, %xmm0
74 # CHECK: insertq %xmm1, %xmm0
Dx86-32.txt646 # CHECK: insertq $6, $5, %xmm1, %xmm0
649 # CHECK: insertq %xmm1, %xmm0
/external/llvm/lib/Target/X86/
DX86InstrSSE.td7776 "insertq\t{$idx, $len, $src2, $src|$src, $src2, $len, $idx}",
7781 "insertq\t{$mask, $src|$src, $mask}",