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Searched refs:is64BitVector (Results 1 – 8 of 8) sorted by relevance

/external/llvm/include/llvm/CodeGen/
DValueTypes.h143 bool is64BitVector() const { in is64BitVector() function
144 return isSimple() ? V.is64BitVector() : isExtended64BitVector(); in is64BitVector()
DMachineValueType.h233 bool is64BitVector() const { in is64BitVector() function
/external/llvm/lib/Target/ARM/
DARMISelDAGToDAG.cpp273 bool is64BitVector);
1684 unsigned NumVecs, bool is64BitVector) { in GetVLDSTAlign() argument
1686 if (!is64BitVector && NumVecs < 3) in GetVLDSTAlign()
1818 bool is64BitVector = VT.is64BitVector(); in SelectVLD() local
1819 Align = GetVLDSTAlign(Align, dl, NumVecs, is64BitVector); in SelectVLD()
1846 if (!is64BitVector) in SelectVLD()
1862 if (is64BitVector || NumVecs <= 2) { in SelectVLD()
1863 unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] : in SelectVLD()
1927 unsigned Sub0 = (is64BitVector ? ARM::dsub_0 : ARM::qsub_0); in SelectVLD()
1955 bool is64BitVector = VT.is64BitVector(); in SelectVST() local
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DARMISelLowering.cpp4393 EVT VT8Bit = VT.is64BitVector() ? MVT::v8i8 : MVT::v16i8; in LowerCTTZ()
4398 EVT VT16Bit = VT.is64BitVector() ? MVT::v4i16 : MVT::v8i16; in LowerCTTZ()
4405 EVT VT32Bit = VT.is64BitVector() ? MVT::v2i32 : MVT::v4i32; in LowerCTTZ()
4443 EVT VT8Bit = VT.is64BitVector() ? MVT::v8i8 : MVT::v16i8; in getCTPOP16BitCounts()
4466 if (VT.is64BitVector()) { in lowerCTPOP16BitElements()
4500 EVT VT16Bit = VT.is64BitVector() ? MVT::v4i16 : MVT::v8i16; in lowerCTPOP32BitElements()
4508 if (VT.is64BitVector()) { in lowerCTPOP32BitElements()
5186 if (VT.is64BitVector() && EltSz == 32) in isVUZPMask()
5222 if (VT.is64BitVector() && EltSz == 32) in isVUZP_v_undef_Mask()
5260 if (VT.is64BitVector() && EltSz == 32) in isVZIPMask()
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/external/llvm/lib/Target/AArch64/
DAArch64CallingConvention.h96 else if (LocVT.SimpleTy == MVT::f64 || LocVT.is64BitVector()) in CC_AArch64_Custom_Block()
DAArch64ISelLowering.cpp2192 assert(Op0.getValueType().is64BitVector() && in LowerMUL()
2193 Op1.getValueType().is64BitVector() && in LowerMUL()
2445 else if (RegVT == MVT::f64 || RegVT.is64BitVector()) in LowerFormalArguments()
6454 (VT.is128BitVector() || VT.is64BitVector())) { in isShuffleMaskLegal()
8054 if (!NarrowTy.is64BitVector()) in tryExtendDUPToExtractHigh()
8271 assert(LHS.getValueType().is64BitVector() && in tryCombineLongOpWithDup()
8272 RHS.getValueType().is64BitVector() && in tryCombineLongOpWithDup()
DAArch64FastISel.cpp2837 else if ((VT >= MVT::f16 && VT <= MVT::f64) || VT.is64BitVector() || in fastLowerArguments()
2881 } else if ((VT == MVT::f64) || VT.is64BitVector()) { in fastLowerArguments()
DAArch64ISelDAGToDAG.cpp1099 } else if (VT == MVT::f64 || VT.is64BitVector()) { in SelectIndexedLoad()