| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMMCCodeEmitter.cpp | 567 bool isAdd = true; in EncodeAddrModeOpValues() local
572 isAdd = false; in EncodeAddrModeOpValues()
578 isAdd = false; in EncodeAddrModeOpValues()
582 return isAdd; in EncodeAddrModeOpValues()
887 bool isAdd = true; in getAddrModeImm12OpValue() local
896 isAdd = false ; // 'U' bit is set as part of the fixup. in getAddrModeImm12OpValue()
911 isAdd = false; in getAddrModeImm12OpValue()
914 isAdd = false; in getAddrModeImm12OpValue()
919 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups, STI); in getAddrModeImm12OpValue()
923 if (isAdd) in getAddrModeImm12OpValue()
[all …]
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| D | ARMAsmBackend.cpp | 393 bool isAdd = true; in adjustFixupValue() local
396 isAdd = false; in adjustFixupValue()
402 Value |= isAdd << 23; in adjustFixupValue()
587 bool isAdd = true; in adjustFixupValue() local
590 isAdd = false; in adjustFixupValue()
598 return Value | (isAdd << 23); in adjustFixupValue()
607 bool isAdd = true; in adjustFixupValue() local
610 isAdd = false; in adjustFixupValue()
618 Value |= isAdd << 23; in adjustFixupValue()
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| /external/apache-commons-math/src/main/java/org/apache/commons/math/fraction/ |
| D | Fraction.java | 476 private Fraction addSub(Fraction fraction, boolean isAdd) { in addSub() argument
482 return isAdd ? fraction : fraction.negate(); in addSub()
495 (isAdd ? MathUtils.addAndCheck(uvp, upv) : in addSub()
506 BigInteger t = isAdd ? uvp.add(upv) : uvp.subtract(upv); in addSub()
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| /external/smali/dexlib2/src/main/java/org/jf/dexlib2/util/ |
| D | SyntheticAccessorFSM.java | 555 boolean isAdd = ((mathOp == ADD) && !negativeConstant) || in getIncrementType()
559 if (isAdd) { in getIncrementType()
565 if (isAdd) { in getIncrementType()
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| /external/smali/dexlib2/src/main/ragel/ |
| D | SyntheticAccessorFSM.rl | 252 boolean isAdd = ((mathOp == ADD) && !negativeConstant) ||
256 if (isAdd) {
262 if (isAdd) {
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| /external/valgrind/VEX/priv/ |
| D | host_arm64_defs.h | 536 Bool isAdd; member
883 extern ARM64Instr* ARM64Instr_Arith ( HReg, HReg, ARM64RIA*, Bool isAdd );
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| D | host_ppc_defs.c | 734 PPCInstr* PPCInstr_AddSubC ( Bool isAdd, Bool setC, in PPCInstr_AddSubC() argument
738 i->Pin.AddSubC.isAdd = isAdd; in PPCInstr_AddSubC()
1505 i->Pin.AddSubC.isAdd ? "add" : "sub", in ppPPCInstr()
3942 Bool isAdd = i->Pin.AddSubC.isAdd; in emit_PPCInstr() local
3948 if (isAdd) { in emit_PPCInstr()
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| D | host_arm64_defs.c | 820 HReg argL, ARM64RIA* argR, Bool isAdd ) { in ARM64Instr_Arith() argument
826 i->ARM64in.Arith.isAdd = isAdd; in ARM64Instr_Arith()
1366 vex_printf("%s ", i->ARM64in.Arith.isAdd ? "add" : "sub"); in ppARM64Instr()
3271 i->ARM64in.Arith.isAdd ? X10 : X11, in emit_ARM64Instr()
3280 i->ARM64in.Arith.isAdd ? X100 : X110, in emit_ARM64Instr()
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| D | host_ppc_defs.h | 570 Bool isAdd; /* else sub */ member
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| D | guest_amd64_toIR.c | 15224 static IRTemp math_HADDPS_128 ( IRTemp dV, IRTemp sV, Bool isAdd ) in math_HADDPS_128() argument
15240 assign( res, triop(isAdd ? Iop_Add32Fx4 : Iop_Sub32Fx4, in math_HADDPS_128()
15246 static IRTemp math_HADDPD_128 ( IRTemp dV, IRTemp sV, Bool isAdd ) in math_HADDPD_128() argument
15262 assign( res, triop(isAdd ? Iop_Add64Fx2 : Iop_Sub64Fx2, in math_HADDPD_128()
15320 Bool isAdd = opc == 0x7C; in dis_ESC_0F__SSE3() local
15321 const HChar* str = isAdd ? "add" : "sub"; in dis_ESC_0F__SSE3()
15337 putXMMReg( rG, mkexpr( math_HADDPS_128 ( gV, eV, isAdd ) ) ); in dis_ESC_0F__SSE3()
15345 Bool isAdd = opc == 0x7C; in dis_ESC_0F__SSE3() local
15346 const HChar* str = isAdd ? "add" : "sub"; in dis_ESC_0F__SSE3()
15362 putXMMReg( rG, mkexpr( math_HADDPD_128 ( gV, eV, isAdd ) ) ); in dis_ESC_0F__SSE3()
[all …]
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| D | guest_arm64_toIR.c | 2991 Bool isAdd = INSN(15,15) == 0; in dis_ARM64_data_processing_register() local
2998 binop(isAdd ? Iop_Add64 : Iop_Sub64, in dis_ARM64_data_processing_register()
3004 binop(isAdd ? Iop_Add32 : Iop_Sub32, in dis_ARM64_data_processing_register()
3009 isAdd ? "madd" : "msub", in dis_ARM64_data_processing_register()
3478 Bool isAdd = INSN(15,15) == 0; in dis_ARM64_data_processing_register() local
3492 assign(res, binop(isAdd ? Iop_Add64 : Iop_Sub64, in dis_ARM64_data_processing_register()
3495 DIP("%cm%sl %s, %s, %s, %s\n", isU ? 'u' : 's', isAdd ? "add" : "sub", in dis_ARM64_data_processing_register()
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| D | host_arm64_isel.c | 1512 Bool isAdd = e->Iex.Binop.op == Iop_Add64 in iselIntExpr_R_wrk() local
1517 addInstr(env, ARM64Instr_Arith(dst, argL, argR, isAdd)); in iselIntExpr_R_wrk()
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| D | guest_x86_toIR.c | 11939 Bool isAdd = insn[2] == 0x7C; in disInstr_X86_WRK() local
11940 const HChar* str = isAdd ? "add" : "sub"; in disInstr_X86_WRK()
11967 triop(isAdd ? Iop_Add32Fx4 : Iop_Sub32Fx4, in disInstr_X86_WRK()
11984 Bool isAdd = insn[1] == 0x7C; in disInstr_X86_WRK() local
11985 const HChar* str = isAdd ? "add" : "sub"; in disInstr_X86_WRK()
12013 triop(isAdd ? Iop_Add64Fx2 : Iop_Sub64Fx2, in disInstr_X86_WRK()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonHardwareLoops.cpp | 419 bool isAdd = (UpdOpc == Hexagon::A2_addi || UpdOpc == Hexagon::A2_addp); in findInductionRegister() local
421 if (isAdd) { in findInductionRegister()
1600 bool isAdd = (UpdOpc == Hexagon::A2_addi || UpdOpc == Hexagon::A2_addp); in fixupInductionVariable() local
1602 if (isAdd) { in fixupInductionVariable()
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| /external/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 504 bool isAdd; member
2108 ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0); in addAM3OffsetOperands()
2285 bool isAdd = Imm >= 0; in addPostIdxImm8Operands() local
2287 Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8; in addPostIdxImm8Operands()
2296 bool isAdd = Imm >= 0; in addPostIdxImm8s4Operands() local
2299 Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8; in addPostIdxImm8s4Operands()
2306 Inst.addOperand(MCOperand::createImm(PostIdxReg.isAdd)); in addPostIdxRegOperands()
2314 ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub; in addPostIdxRegShiftedOperands()
2706 CreatePostIdxReg(unsigned RegNum, bool isAdd, ARM_AM::ShiftOpc ShiftTy, in CreatePostIdxReg() argument
2710 Op->PostIdxReg.isAdd = isAdd; in CreatePostIdxReg()
[all …]
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| /external/eclipse-basebuilder/basebuilder-3.6.2/org.eclipse.releng.basebuilder/plugins/org.apache.ant_1.7.1.v20090120-1145/lib/ |
| D | ant-apache-oro.jar | META-INF/
META-INF/MANIFEST.MF
org/
org/apache/
org/ ... |
| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrInfo.td | 2552 // {12} isAdd
2570 // {12} isAdd
2662 // {12} isAdd
2681 // {12} isAdd
2698 // {12} isAdd
2717 // {12} isAdd
2817 // {12} isAdd
2835 // {12} isAdd
2979 // {12} isAdd
2998 // {12} isAdd
[all …]
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| D | ARMInstrFormats.td | 663 // {12} isAdd
681 // {12} isAdd
702 // {12} isAdd
755 // {8} isAdd
|
| /external/owasp/sanitizer/tools/findbugs/lib/ |
| D | commons-lang-2.6.jar | META-INF/
META-INF/MANIFEST.MF
org/
org/apache/
org/ ... |
| /external/guice/extensions/persist/lib/ |
| D | db4o-6.4.14.8131-java5.jar | META-INF/
META-INF/MANIFEST.MF
com/
com/db4o/
com/ ... |
| /external/guice/extensions/struts2/lib/ |
| D | xwork-core-2.2.1.jar | META-INF/
META-INF/MANIFEST.MF
xwork-validator-definition-1.0. ... |