Searched refs:isOperationLegal (Results 1 – 8 of 8) sorted by relevance
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | DAGCombiner.cpp | 995 if (!TLI.isOperationLegal(ISD::ANY_EXTEND, PVT)) in PromoteOperand()
1001 if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT)) in SExtPromoteOperand()
1737 if ((!LegalOperations || TLI.isOperationLegal(ISD::OR, VT)) && in visitADD()
1771 !TLI.isOperationLegal(ISD::SIGN_EXTEND, MVT::i1)) { in visitADD()
1858 if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) in tryFoldToZero()
2501 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { in visitMULHS()
2537 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { in visitMULHU()
2569 TLI.isOperationLegal(HiOp, N->getValueType(1)))) { in SimplifyNodeWithTwoResults()
2585 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType()))) in SimplifyNodeWithTwoResults()
2595 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType()))) in SimplifyNodeWithTwoResults()
[all …]
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| D | TargetLowering.cpp | 1489 (isOperationLegal(ISD::SETCC, newVT) && in SimplifySetCC()
2765 if (IsAfterLegalization ? isOperationLegal(ISD::MULHS, VT) : in BuildSDIV()
2769 else if (IsAfterLegalization ? isOperationLegal(ISD::SMUL_LOHI, VT) : in BuildSDIV()
2843 if (IsAfterLegalization ? isOperationLegal(ISD::MULHU, VT) : in BuildUDIV()
2846 else if (IsAfterLegalization ? isOperationLegal(ISD::UMUL_LOHI, VT) : in BuildUDIV()
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| D | LegalizeIntegerTypes.cpp | 421 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) && in PromoteIntRes_FP_TO_XINT()
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| D | SelectionDAGBuilder.cpp | 8032 if (!TLI.isOperationLegal(ISD::SHL, PTy)) in findBitTestClusters()
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| /external/llvm/include/llvm/Target/ |
| D | TargetLowering.h | 582 bool isOperationLegal(unsigned Op, EVT VT) const { in isOperationLegal() function
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| /external/llvm/lib/Target/AMDGPU/ |
| D | R600ISelLowering.cpp | 1895 if (!isOperationLegal(ISD::BUILD_VECTOR, VT)) in PerformDAGCombine()
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 5442 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT)) in EltsFromConsecutiveLoads()
13972 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) { in EmitTest()
17893 TLI.isOperationLegal(ISD::CTLZ, VT)) { in LowerCTTZ()
23562 TLI.isOperationLegal(Opcode, VT)) { in PerformShuffleCombine()
23857 if (TLI.isOperationLegal(ISD::SRA, MVT::i64)) { in PerformEXTRACT_VECTOR_ELTCombine()
27445 if (TLI.isOperationLegal(ISD::UINT_TO_FP, DstVT)) in PerformUINT_TO_FPCombine()
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZISelLowering.cpp | 4128 if (isOperationLegal(ISD::SCALAR_TO_VECTOR, VT) && isScalarToVector(Op)) in lowerBUILD_VECTOR()
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