| /external/llvm/test/MC/AArch64/ |
| D | neon-simd-ldst-one-elem.s | 8 ld1r { v0.16b }, [x0]
9 ld1r { v15.8h }, [x15]
10 ld1r { v31.4s }, [sp]
11 ld1r { v0.2d }, [x0]
12 ld1r { v0.8b }, [x0]
13 ld1r { v15.4h }, [x15]
14 ld1r { v31.2s }, [sp]
15 ld1r { v0.1d }, [x0]
169 ld1r { v0.16b }, [x0], #1
170 ld1r { v15.8h }, [x15], #2
[all …]
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| D | arm64-simd-ldst.s | 850 ld1r: label
851 ld1r.8b {v4}, [x2]
852 ld1r.8b {v4}, [x2], x3
853 ld1r.16b {v4}, [x2]
854 ld1r.16b {v4}, [x2], x3
855 ld1r.4h {v4}, [x2]
856 ld1r.4h {v4}, [x2], x3
857 ld1r.8h {v4}, [x2]
858 ld1r.8h {v4}, [x2], x3
859 ld1r.2s {v4}, [x2]
[all …]
|
| D | neon-diagnostics.s | 4193 ld1r {x1}, [x0]
4252 ld1r {v15.8h}, [x15], #5
|
| /external/llvm/test/CodeGen/AArch64/ |
| D | arm64-neon-simd-ldst-one.ll | 127 ; CHECK: ld1r {{{ ?v[0-9]+.16b ?}}}, [x0]
137 ; CHECK: ld1r {{{ ?v[0-9]+.8h ?}}}, [x0]
147 ; CHECK: ld1r {{{ ?v[0-9]+.4s ?}}}, [x0]
157 ; CHECK: ld1r {{{ ?v[0-9]+.2d ?}}}, [x0]
167 ; CHECK: ld1r {{{ ?v[0-9]+.4s ?}}}, [x0]
177 ; CHECK: ld1r {{{ ?v[0-9]+.2d ?}}}, [x0]
187 ; CHECK: ld1r {{{ ?v[0-9]+.8b ?}}}, [x0]
197 ; CHECK: ld1r {{{ ?v[0-9]+.4h ?}}}, [x0]
207 ; CHECK: ld1r {{{ ?v[0-9]+.2s ?}}}, [x0]
226 ; CHECK: ld1r {{{ ?v[0-9]+.2s ?}}}, [x0]
|
| D | arm64-ld1.ll | 450 ; CHECK: ld1r.8b { v0 }, [x0]
467 ; CHECK: ld1r.16b { v0 }, [x0]
492 ; CHECK: ld1r.4h { v0 }, [x0]
505 ; CHECK: ld1r.8h { v0 }, [x0]
522 ; CHECK: ld1r.2s { v0 }, [x0]
533 ; CHECK: ld1r.4s { v0 }, [x0]
546 ; CHECK: ld1r.2d { v0 }, [x0]
912 ; Add rdar://13098923 test case: vld1_dup_u32 doesn't generate ld1r.2s
916 ; CHECK: ld1r.2s { [[ARG1:v[0-9]+]] }, [x0]
917 ; CHECK-NEXT: ld1r.2s { [[ARG2:v[0-9]+]] }, [x1]
[all …]
|
| D | fp16-vector-load-store.ll | 24 ; CHECK: ld1r { v0.4h }, [x0]
35 ; CHECK: ld1r { v0.8h }, [x0]
|
| D | arm64-indexed-vector-ldst.ll | 5694 ; CHECK: ld1r.16b { v0 }, [x0], #1
5719 ; CHECK: ld1r.16b { v0 }, [x0], x{{[0-9]+}}
5744 ; CHECK: ld1r.8b { v0 }, [x0], #1
5761 ; CHECK: ld1r.8b { v0 }, [x0], x{{[0-9]+}}
5778 ; CHECK: ld1r.8h { v0 }, [x0], #2
5795 ; CHECK: ld1r.8h { v0 }, [x0], x{{[0-9]+}}
5812 ; CHECK: ld1r.4h { v0 }, [x0], #2
5825 ; CHECK: ld1r.4h { v0 }, [x0], x{{[0-9]+}}
5838 ; CHECK: ld1r.4s { v0 }, [x0], #4
5851 ; CHECK: ld1r.4s { v0 }, [x0], x{{[0-9]+}}
[all …]
|
| /external/llvm/test/MC/Disassembler/AArch64/ |
| D | arm64-advsimd.txt | 924 # CHECK: ld1r.8b { v1 }, [x1]
925 # CHECK: ld1r.8b { v1 }, [x1], x2
926 # CHECK: ld1r.4h { v4 }, [x3]
927 # CHECK: ld1r.4h { v4 }, [x3], x5
928 # CHECK: ld1r.2s { v9 }, [x5]
929 # CHECK: ld1r.2s { v9 }, [x5], x6
930 # CHECK: ld1r.1d { v12 }, [x7]
931 # CHECK: ld1r.1d { v12 }, [x7], x8
938 # CHECK: ld1r.8b { v1 }, [x1], #1
939 # CHECK: ld1r.4h { v1 }, [x1], #2
[all …]
|
| D | neon-instructions.txt | 2082 # CHECK: ld1r { v0.16b }, [x0]
2083 # CHECK: ld1r { v15.8h }, [x15]
2124 # CHECK: ld1r { v0.16b }, [x0], #1
2125 # CHECK: ld1r { v15.8h }, [x15], #2
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrFormats.td | 8585 // E.g. "ld1r { v0.8b }, [x1], #1"
8586 // "ld1r.8b\t$Vt, [$Rn], #1"
8595 // E.g. "ld1r.8b { v0 }, [x1], #1"
8596 // "ld1r.8b\t$Vt, [$Rn], #1"
8605 // E.g. "ld1r.8b { v0 }, [x1]"
8606 // "ld1r.8b\t$Vt, [$Rn]"
8614 // E.g. "ld1r.8b { v0 }, [x1], x2"
8615 // "ld1r.8b\t$Vt, [$Rn], $Xm"
|
| D | AArch64InstrInfo.td | 4977 defm LD1R : SIMDLdR<0, 0b110, 0, "ld1r", "One", 1, 2, 4, 8>;
|
| /external/vixl/src/vixl/a64/ |
| D | simulator-a64.h | 1334 void ld1r(VectorFormat vform,
|
| D | macro-assembler-a64.h | 2565 ld1r(vt, src); in Ld1r()
|
| D | assembler-a64.h | 2808 void ld1r(const VRegister& vt,
|
| D | simulator-a64.cc | 3167 ld1r(vf, vreg(rt), addr); in NEONLoadStoreSingleStructHelper()
|
| D | logic-a64.cc | 409 void Simulator::ld1r(VectorFormat vform, in ld1r() function in vixl::Simulator
|
| D | assembler-a64.cc | 2326 void Assembler::ld1r(const VRegister& vt, in ld1r() function in vixl::Assembler
|
| /external/vixl/doc/ |
| D | supported-instructions.md | 2559 void ld1r(const VRegister& vt,
|
| /external/valgrind/none/tests/arm64/ |
| D | memory.stdout.exp | 17192 ld1r {v17.2d}, [x5] with x5 = middle_of_block+3, x6=-5
17222 ld1r {v17.1d}, [x5] with x5 = middle_of_block+3, x6=-4
17252 ld1r {v17.4s}, [x5] with x5 = middle_of_block+3, x6=-3
17282 ld1r {v17.2s}, [x5] with x5 = middle_of_block+3, x6=-2
17312 ld1r {v17.8h}, [x5] with x5 = middle_of_block+3, x6=-1
17342 ld1r {v17.4h}, [x5] with x5 = middle_of_block+3, x6=1
17372 ld1r {v17.16b}, [x5] with x5 = middle_of_block+3, x6=2
17402 ld1r {v17.8b}, [x5] with x5 = middle_of_block+3, x6=3
17432 ld1r {v17.2d}, [x5], #8 with x5 = middle_of_block+3, x6=-5
17462 ld1r {v17.1d}, [x5], #8 with x5 = middle_of_block+3, x6=-4
[all …]
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| /external/hyphenation-patterns/nb/ |
| D | hyph-nb.pat.txt | 12514 ld1rø
|
| /external/hyphenation-patterns/nn/ |
| D | hyph-nn.pat.txt | 12514 ld1rø
|