| /external/llvm/test/MC/AArch64/ |
| D | neon-simd-ldst-one-elem.s | 29 ld2r { v0.16b, v1.16b }, [x0]
30 ld2r { v15.8h, v16.8h }, [x15]
31 ld2r { v31.4s, v0.4s }, [sp]
32 ld2r { v0.2d, v1.2d }, [x0]
33 ld2r { v0.8b, v1.8b }, [x0]
34 ld2r { v15.4h, v16.4h }, [x15]
35 ld2r { v31.2s, v0.2s }, [sp]
36 ld2r { v31.1d, v0.1d }, [sp]
190 ld2r { v0.16b, v1.16b }, [x0], #2
191 ld2r { v15.8h, v16.8h }, [x15], #4
[all …]
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| D | arm64-simd-ldst.s | 904 ld2r: label
905 ld2r.8b {v4, v5}, [x2]
906 ld2r.8b {v4, v5}, [x2], x3
907 ld2r.16b {v4, v5}, [x2]
908 ld2r.16b {v4, v5}, [x2], x3
909 ld2r.4h {v4, v5}, [x2]
910 ld2r.4h {v4, v5}, [x2], x3
911 ld2r.8h {v4, v5}, [x2]
912 ld2r.8h {v4, v5}, [x2], x3
913 ld2r.2s {v4, v5}, [x2]
[all …]
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| D | neon-diagnostics.s | 4194 ld2r {v31.4s, v0.2s}, [sp]
4253 ld2r {v0.2d, v1.2d}, [x0], #7
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| /external/llvm/test/CodeGen/AArch64/ |
| D | arm64-ld1.ll | 557 ; CHECK: ld2r.8b { v0, v1 }, [x0]
559 %tmp2 = call %struct.__neon_int8x8x2_t @llvm.aarch64.neon.ld2r.v8i8.p0i8(i8* %A)
581 declare %struct.__neon_int8x8x2_t @llvm.aarch64.neon.ld2r.v8i8.p0i8(i8*) nounwind readonly
588 ; CHECK: ld2r.16b { v0, v1 }, [x0]
590 %tmp2 = call %struct.__neon_int8x16x2_t @llvm.aarch64.neon.ld2r.v16i8.p0i8(i8* %A)
612 declare %struct.__neon_int8x16x2_t @llvm.aarch64.neon.ld2r.v16i8.p0i8(i8*) nounwind readonly
619 ; CHECK: ld2r.4h { v0, v1 }, [x0]
621 %tmp2 = call %struct.__neon_int16x4x2_t @llvm.aarch64.neon.ld2r.v4i16.p0i16(i16* %A)
643 declare %struct.__neon_int16x4x2_t @llvm.aarch64.neon.ld2r.v4i16.p0i16(i16*) nounwind readonly
650 ; CHECK: ld2r.8h { v0, v1 }, [x0]
[all …]
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| D | fp16-vector-load-store.ll | 224 declare { <4 x half>, <4 x half> } @llvm.aarch64.neon.ld2r.v4f16.p0f16(half*)
227 declare { <8 x half>, <8 x half> } @llvm.aarch64.neon.ld2r.v8f16.p0f16(half*)
234 ; CHECK: ld2r { v0.4h, v1.4h }, [x0]
236 %0 = tail call { <4 x half>, <4 x half> } @llvm.aarch64.neon.ld2r.v4f16.p0f16(half* %a)
261 ; CHECK: ld2r { v0.8h, v1.8h }, [x0]
263 %0 = tail call { <8 x half>, <8 x half> } @llvm.aarch64.neon.ld2r.v8f16.p0f16(half* %a)
|
| D | arm64-indexed-vector-ldst.ll | 2128 ;CHECK: ld2r.16b { v0, v1 }, [x0], #2
2129 %ld2 = call { <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld2r.v16i8.p0i8(i8* %A)
2137 ;CHECK: ld2r.16b { v0, v1 }, [x0], x{{[0-9]+}}
2138 %ld2 = call { <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld2r.v16i8.p0i8(i8* %A)
2144 declare { <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld2r.v16i8.p0i8(i8*) nounwind readonly
2149 ;CHECK: ld2r.8b { v0, v1 }, [x0], #2
2150 %ld2 = call { <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld2r.v8i8.p0i8(i8* %A)
2158 ;CHECK: ld2r.8b { v0, v1 }, [x0], x{{[0-9]+}}
2159 %ld2 = call { <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld2r.v8i8.p0i8(i8* %A)
2165 declare { <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld2r.v8i8.p0i8(i8*) nounwind readonly
[all …]
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| /external/llvm/test/MC/Disassembler/AArch64/ |
| D | arm64-advsimd.txt | 1074 # CHECK: ld2r.8b { v1, v2 }, [x1]
1075 # CHECK: ld2r.8b { v1, v2 }, [x1], x2
1076 # CHECK: ld2r.16b { v1, v2 }, [x1]
1077 # CHECK: ld2r.16b { v1, v2 }, [x1], x2
1078 # CHECK: ld2r.4h { v1, v2 }, [x1]
1079 # CHECK: ld2r.4h { v1, v2 }, [x1], x2
1080 # CHECK: ld2r.8h { v1, v2 }, [x1]
1081 # CHECK: ld2r.8h { v1, v2 }, [x1], x2
1082 # CHECK: ld2r.2s { v1, v2 }, [x1]
1083 # CHECK: ld2r.2s { v1, v2 }, [x1], x2
[all …]
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| D | neon-instructions.txt | 2084 # CHECK: ld2r { v31.4s, v0.4s }, [sp]
2085 # CHECK: ld2r { v0.2d, v1.2d }, [x0]
2126 # CHECK: ld2r { v31.4s, v0.4s }, [sp], #8
2127 # CHECK: ld2r { v0.2d, v1.2d }, [x0], #16
|
| /external/vixl/src/vixl/a64/ |
| D | simulator-a64.h | 1346 void ld2r(VectorFormat vform,
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| D | macro-assembler-a64.h | 2587 ld2r(vt, vt2, src); in Ld2r()
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| D | assembler-a64.h | 2823 void ld2r(const VRegister& vt,
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| D | simulator-a64.cc | 3176 ld2r(vf, vreg(rt), vreg(rt2), addr); in NEONLoadStoreSingleStructHelper()
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| D | logic-a64.cc | 449 void Simulator::ld2r(VectorFormat vform, in ld2r() function in vixl::Simulator
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| D | assembler-a64.cc | 2096 void Assembler::ld2r(const VRegister& vt, in ld2r() function in vixl::Assembler
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| /external/vixl/doc/ |
| D | supported-instructions.md | 2586 void ld2r(const VRegister& vt,
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| /external/valgrind/none/tests/arm64/ |
| D | memory.stdout.exp | 17913 ld2r {v17.2d , v18.2d }, [x5] with x5 = middle_of_block+3, x6=-5
17943 ld2r {v18.1d , v19.1d }, [x5] with x5 = middle_of_block+3, x6=-4
17973 ld2r {v19.4s , v20.4s }, [x5] with x5 = middle_of_block+3, x6=-3
18003 ld2r {v17.2s , v18.2s }, [x5] with x5 = middle_of_block+3, x6=-2
18033 ld2r {v18.8h , v19.8h }, [x5] with x5 = middle_of_block+3, x6=-1
18063 ld2r {v19.4h , v20.4h }, [x5] with x5 = middle_of_block+3, x6=1
18093 ld2r {v17.16b, v18.16b}, [x5] with x5 = middle_of_block+3, x6=2
18123 ld2r {v18.8b , v19.8b }, [x5] with x5 = middle_of_block+3, x6=3
18153 ld2r {v19.2d , v20.2d }, [x5], #16 with x5 = middle_of_block+3, x6=-5
18183 ld2r {v17.1d , v18.1d }, [x5], #16 with x5 = middle_of_block+3, x6=-4
[all …]
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.td | 4978 defm LD2R : SIMDLdR<1, 0b110, 0, "ld2r", "Two", 2, 4, 8, 16>;
|
| /external/hyphenation-patterns/hu/ |
| D | hyph-hu.pat.txt | 30358 ld2rót
|