| /external/llvm/test/MC/AArch64/ |
| D | neon-simd-ldst-one-elem.s | 46 ld3r { v0.16b, v1.16b, v2.16b }, [x0]
47 ld3r { v15.8h, v16.8h, v17.8h }, [x15]
48 ld3r { v31.4s, v0.4s, v1.4s }, [sp]
49 ld3r { v0.2d, v1.2d, v2.2d }, [x0]
50 ld3r { v0.8b, v1.8b, v2.8b }, [x0]
51 ld3r { v15.4h, v16.4h, v17.4h }, [x15]
52 ld3r { v31.2s, v0.2s, v1.2s }, [sp]
53 ld3r { v31.1d, v0.1d, v1.1d }, [sp]
207 ld3r { v0.16b, v1.16b, v2.16b }, [x0], x9
208 ld3r { v15.8h, v16.8h, v17.8h }, [x15], x6
[all …]
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| D | arm64-simd-ldst.s | 958 ld3r: label
959 ld3r.8b {v4, v5, v6}, [x2]
960 ld3r.8b {v4, v5, v6}, [x2], x3
961 ld3r.16b {v4, v5, v6}, [x2]
962 ld3r.16b {v4, v5, v6}, [x2], x3
963 ld3r.4h {v4, v5, v6}, [x2]
964 ld3r.4h {v4, v5, v6}, [x2], x3
965 ld3r.8h {v4, v5, v6}, [x2]
966 ld3r.8h {v4, v5, v6}, [x2], x3
967 ld3r.2s {v4, v5, v6}, [x2]
[all …]
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| D | neon-diagnostics.s | 4195 ld3r {v0.8b, v1.8b, v2.8b, v3.8b}, [x0]
4254 ld3r {v15.4h, v16.4h, v17.4h}, [x15], #1
|
| /external/llvm/test/CodeGen/AArch64/ |
| D | arm64-ld1.ll | 566 ; CHECK: ld3r.8b { v0, v1, v2 }, [x0]
568 %tmp2 = call %struct.__neon_int8x8x3_t @llvm.aarch64.neon.ld3r.v8i8.p0i8(i8* %A)
582 declare %struct.__neon_int8x8x3_t @llvm.aarch64.neon.ld3r.v8i8.p0i8(i8*) nounwind readonly
597 ; CHECK: ld3r.16b { v0, v1, v2 }, [x0]
599 %tmp2 = call %struct.__neon_int8x16x3_t @llvm.aarch64.neon.ld3r.v16i8.p0i8(i8* %A)
613 declare %struct.__neon_int8x16x3_t @llvm.aarch64.neon.ld3r.v16i8.p0i8(i8*) nounwind readonly
628 ; CHECK: ld3r.4h { v0, v1, v2 }, [x0]
630 %tmp2 = call %struct.__neon_int16x4x3_t @llvm.aarch64.neon.ld3r.v4i16.p0i16(i16* %A)
644 declare %struct.__neon_int16x4x3_t @llvm.aarch64.neon.ld3r.v4i16.p0i16(i16*) nounwind readonly
659 ; CHECK: ld3r.8h { v0, v1, v2 }, [x0]
[all …]
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| D | fp16-vector-load-store.ll | 225 declare { <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld3r.v4f16.p0f16(half*)
228 declare { <8 x half>, <8 x half>, <8 x half> } @llvm.aarch64.neon.ld3r.v8f16.p0f16(half*)
243 ; CHECK: ld3r { v0.4h, v1.4h, v2.4h }, [x0]
245 …%0 = tail call { <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld3r.v4f16.p0f16(half* %a)
270 ; CHECK: ld3r { v0.8h, v1.8h, v2.8h }, [x0]
272 …%0 = tail call { <8 x half>, <8 x half>, <8 x half> } @llvm.aarch64.neon.ld3r.v8f16.p0f16(half* %a)
|
| D | arm64-indexed-vector-ldst.ll | 2376 ;CHECK: ld3r.16b { v0, v1, v2 }, [x0], #3
2377 %ld3 = call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld3r.v16i8.p0i8(i8* %A)
2385 ;CHECK: ld3r.16b { v0, v1, v2 }, [x0], x{{[0-9]+}}
2386 %ld3 = call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld3r.v16i8.p0i8(i8* %A)
2392 declare { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld3r.v16i8.p0i8(i8*) nounwind readon…
2397 ;CHECK: ld3r.8b { v0, v1, v2 }, [x0], #3
2398 %ld3 = call { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld3r.v8i8.p0i8(i8* %A)
2406 ;CHECK: ld3r.8b { v0, v1, v2 }, [x0], x{{[0-9]+}}
2407 %ld3 = call { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld3r.v8i8.p0i8(i8* %A)
2413 declare { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld3r.v8i8.p0i8(i8*) nounwind readonly
[all …]
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| /external/llvm/test/MC/Disassembler/AArch64/ |
| D | arm64-advsimd.txt | 1260 # CHECK: ld3r.8b { v1, v2, v3 }, [x1]
1261 # CHECK: ld3r.8b { v1, v2, v3 }, [x1], x2
1262 # CHECK: ld3r.16b { v1, v2, v3 }, [x1]
1263 # CHECK: ld3r.16b { v1, v2, v3 }, [x1], x2
1264 # CHECK: ld3r.4h { v1, v2, v3 }, [x1]
1265 # CHECK: ld3r.4h { v1, v2, v3 }, [x1], x2
1266 # CHECK: ld3r.8h { v1, v2, v3 }, [x1]
1267 # CHECK: ld3r.8h { v1, v2, v3 }, [x1], x2
1268 # CHECK: ld3r.2s { v1, v2, v3 }, [x1]
1269 # CHECK: ld3r.2s { v1, v2, v3 }, [x1], x2
[all …]
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| D | neon-instructions.txt | 2086 # CHECK: ld3r { v0.8b, v1.8b, v2.8b }, [x0]
2087 # CHECK: ld3r { v15.4h, v16.4h, v17.4h }, [x15]
2128 # CHECK: ld3r { v0.8b, v1.8b, v2.8b }, [x0], #3
2129 # CHECK: ld3r { v15.4h, v16.4h, v17.4h }, [x15], #6
|
| /external/vixl/src/vixl/a64/ |
| D | simulator-a64.h | 1361 void ld3r(VectorFormat vform,
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| D | macro-assembler-a64.h | 2612 ld3r(vt, vt2, vt3, src); in Ld3r()
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| D | assembler-a64.h | 2841 void ld3r(const VRegister& vt,
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| D | simulator-a64.cc | 3186 ld3r(vf, vreg(rt), vreg(rt2), vreg(rt3), addr); in NEONLoadStoreSingleStructHelper()
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| D | logic-a64.cc | 502 void Simulator::ld3r(VectorFormat vform, in ld3r() function in vixl::Simulator
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| D | assembler-a64.cc | 2129 void Assembler::ld3r(const VRegister& vt, in ld3r() function in vixl::Assembler
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| /external/vixl/doc/ |
| D | supported-instructions.md | 2616 void ld3r(const VRegister& vt,
|
| /external/valgrind/none/tests/arm64/ |
| D | memory.stdout.exp | 18634 ld3r {v17.2d , v18.2d , v19.2d }, [x5] with x5 = middle_of_block+3, x6=-5
18664 ld3r {v18.1d , v19.1d , v20.1d }, [x5] with x5 = middle_of_block+3, x6=-4
18694 ld3r {v17.4s , v18.4s , v19.4s }, [x5] with x5 = middle_of_block+3, x6=-3
18724 ld3r {v18.2s , v19.2s , v20.2s }, [x5] with x5 = middle_of_block+3, x6=-2
18754 ld3r {v17.8h , v18.8h , v19.8h }, [x5] with x5 = middle_of_block+3, x6=-5
18784 ld3r {v18.4h , v19.4h , v20.4h }, [x5] with x5 = middle_of_block+3, x6=-4
18814 ld3r {v17.16b, v18.16b, v19.16b}, [x5] with x5 = middle_of_block+3, x6=-3
18844 ld3r {v18.8b , v19.8b , v20.8b }, [x5] with x5 = middle_of_block+3, x6=-2
18874 ld3r {v17.2d , v18.2d , v19.2d }, [x5], #24 with x5 = middle_of_block+3, x6=-5
18904 ld3r {v18.1d , v19.1d , v20.1d }, [x5], #24 with x5 = middle_of_block+3, x6=-4
[all …]
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| /external/hyphenation-patterns/de/ |
| D | hyph-de-1996.pat.txt | 9867 ld3r
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| D | hyph-de-1901.pat.txt | 10024 ld3r
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| D | hyph-de-ch-1901.pat.txt | 9919 ld3r
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.td | 4979 defm LD3R : SIMDLdR<0, 0b111, 0, "ld3r", "Three", 3, 6, 12, 24>;
|