| /external/llvm/test/MC/AArch64/ |
| D | neon-simd-ldst-one-elem.s | 63 ld4r { v0.16b, v1.16b, v2.16b, v3.16b }, [x0]
64 ld4r { v15.8h, v16.8h, v17.8h, v18.8h }, [x15]
65 ld4r { v31.4s, v0.4s, v1.4s, v2.4s }, [sp]
66 ld4r { v0.2d, v1.2d, v2.2d, v3.2d }, [x0]
67 ld4r { v0.8b, v1.8b, v2.8b, v3.8b }, [x0]
68 ld4r { v15.4h, v16.4h, v17.4h, v18.4h }, [x15]
69 ld4r { v31.2s, v0.2s, v1.2s, v2.2s }, [sp]
70 ld4r { v31.1d, v0.1d, v1.1d, v2.1d }, [sp]
224 ld4r { v0.16b, v1.16b, v2.16b, v3.16b }, [x0], #4
225 ld4r { v15.8h, v16.8h, v17.8h, v18.8h }, [x15], #8
[all …]
|
| D | arm64-simd-ldst.s | 1012 ld4r: label
1013 ld4r.8b {v4, v5, v6, v7}, [x2]
1014 ld4r.8b {v4, v5, v6, v7}, [x2], x3
1015 ld4r.16b {v4, v5, v6, v7}, [x2]
1016 ld4r.16b {v4, v5, v6, v7}, [x2], x3
1017 ld4r.4h {v4, v5, v6, v7}, [x2]
1018 ld4r.4h {v4, v5, v6, v7}, [x2], x3
1019 ld4r.8h {v4, v5, v6, v7}, [x2]
1020 ld4r.8h {v4, v5, v6, v7}, [x2], x3
1021 ld4r.2s {v4, v5, v6, v7}, [x2]
[all …]
|
| D | neon-diagnostics.s | 4196 ld4r {v31.2s, v0.2s, v1.2d, v2.2s}, [sp]
4255 ld4r {v31.1d, v0.1d, v1.1d, v2.1d}, [sp], sp
|
| /external/llvm/test/CodeGen/AArch64/ |
| D | arm64-ld1.ll | 575 ; CHECK: ld4r.8b { v0, v1, v2, v3 }, [x0]
577 %tmp2 = call %struct.__neon_int8x8x4_t @llvm.aarch64.neon.ld4r.v8i8.p0i8(i8* %A)
583 declare %struct.__neon_int8x8x4_t @llvm.aarch64.neon.ld4r.v8i8.p0i8(i8*) nounwind readonly
606 ; CHECK: ld4r.16b { v0, v1, v2, v3 }, [x0]
608 %tmp2 = call %struct.__neon_int8x16x4_t @llvm.aarch64.neon.ld4r.v16i8.p0i8(i8* %A)
614 declare %struct.__neon_int8x16x4_t @llvm.aarch64.neon.ld4r.v16i8.p0i8(i8*) nounwind readonly
637 ; CHECK: ld4r.4h { v0, v1, v2, v3 }, [x0]
639 %tmp2 = call %struct.__neon_int16x4x4_t @llvm.aarch64.neon.ld4r.v4i16.p0i16(i16* %A)
645 declare %struct.__neon_int16x4x4_t @llvm.aarch64.neon.ld4r.v4i16.p0i16(i16*) nounwind readonly
668 ; CHECK: ld4r.8h { v0, v1, v2, v3 }, [x0]
[all …]
|
| D | fp16-vector-load-store.ll | 226 declare { <4 x half>, <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld4r.v4f16.p0f16(half…
229 declare { <8 x half>, <8 x half>, <8 x half>, <8 x half> } @llvm.aarch64.neon.ld4r.v8f16.p0f16(half…
252 ; CHECK: ld4r { v0.4h, v1.4h, v2.4h, v3.4h }, [x0]
254 …%0 = tail call { <4 x half>, <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld4r.v4f16.p0…
279 ; CHECK: ld4r { v0.8h, v1.8h, v2.8h, v3.8h }, [x0]
281 …%0 = tail call { <8 x half>, <8 x half>, <8 x half>, <8 x half> } @llvm.aarch64.neon.ld4r.v8f16.p0…
|
| D | arm64-indexed-vector-ldst.ll | 2624 ;CHECK: ld4r.16b { v0, v1, v2, v3 }, [x0], #4
2625 …%ld4 = call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld4r.v16i8.p0i8(i8* …
2633 ;CHECK: ld4r.16b { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
2634 …%ld4 = call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld4r.v16i8.p0i8(i8* …
2640 declare { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld4r.v16i8.p0i8(i8*) noun…
2645 ;CHECK: ld4r.8b { v0, v1, v2, v3 }, [x0], #4
2646 %ld4 = call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld4r.v8i8.p0i8(i8* %A)
2654 ;CHECK: ld4r.8b { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
2655 %ld4 = call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld4r.v8i8.p0i8(i8* %A)
2661 declare { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld4r.v8i8.p0i8(i8*) nounwind …
[all …]
|
| /external/llvm/test/MC/Disassembler/AArch64/ |
| D | arm64-advsimd.txt | 1446 # CHECK: ld4r.8b { v1, v2, v3, v4 }, [x1]
1447 # CHECK: ld4r.8b { v1, v2, v3, v4 }, [x1], x2
1448 # CHECK: ld4r.16b { v1, v2, v3, v4 }, [x1]
1449 # CHECK: ld4r.16b { v1, v2, v3, v4 }, [x1], x2
1450 # CHECK: ld4r.4h { v1, v2, v3, v4 }, [x1]
1451 # CHECK: ld4r.4h { v1, v2, v3, v4 }, [x1], x2
1452 # CHECK: ld4r.8h { v1, v2, v3, v4 }, [x1]
1453 # CHECK: ld4r.8h { v1, v2, v3, v4 }, [x1], x2
1454 # CHECK: ld4r.2s { v1, v2, v3, v4 }, [x1]
1455 # CHECK: ld4r.2s { v1, v2, v3, v4 }, [x1], x2
[all …]
|
| D | neon-instructions.txt | 2088 # CHECK: ld4r { v31.2s, v0.2s, v1.2s, v2.2s }, [sp]
2089 # CHECK: ld4r { v31.1d, v0.1d, v1.1d, v2.1d }, [sp]
2130 # CHECK: ld4r { v31.2s, v0.2s, v1.2s, v2.2s }, [sp], x30
2131 # CHECK: ld4r { v31.1d, v0.1d, v1.1d, v2.1d }, [sp], x7
|
| /external/vixl/src/vixl/a64/ |
| D | simulator-a64.h | 1379 void ld4r(VectorFormat vform,
|
| D | macro-assembler-a64.h | 2640 ld4r(vt, vt2, vt3, vt4, src); in Ld4r()
|
| D | assembler-a64.h | 2862 void ld4r(const VRegister& vt,
|
| D | simulator-a64.cc | 3197 ld4r(vf, vreg(rt), vreg(rt2), vreg(rt3), vreg(rt4), addr); in NEONLoadStoreSingleStructHelper()
|
| D | logic-a64.cc | 568 void Simulator::ld4r(VectorFormat vform, in ld4r() function in vixl::Simulator
|
| D | assembler-a64.cc | 2165 void Assembler::ld4r(const VRegister& vt, in ld4r() function in vixl::Assembler
|
| /external/vixl/doc/ |
| D | supported-instructions.md | 2649 void ld4r(const VRegister& vt,
|
| /external/valgrind/none/tests/arm64/ |
| D | memory.stdout.exp | 19355 ld4r {v17.2d , v18.2d , v19.2d , v20.2d }, [x5] with x5 = middle_of_block+3, x6=-5
19385 ld4r {v17.1d , v18.1d , v19.1d , v20.1d }, [x5] with x5 = middle_of_block+3, x6=-4
19415 ld4r {v17.4s , v18.4s , v19.4s , v20.4s }, [x5] with x5 = middle_of_block+3, x6=-3
19445 ld4r {v17.2s , v18.2s , v19.2s , v20.2s }, [x5] with x5 = middle_of_block+3, x6=-2
19475 ld4r {v17.8h , v18.8h , v19.8h , v20.8h }, [x5] with x5 = middle_of_block+3, x6=-5
19505 ld4r {v17.4h , v18.4h , v19.4h , v20.4h }, [x5] with x5 = middle_of_block+3, x6=-4
19535 ld4r {v17.16b, v18.16b, v19.16b, v20.16b}, [x5] with x5 = middle_of_block+3, x6=-3
19565 ld4r {v17.8b , v18.8b , v19.8b , v20.8b }, [x5] with x5 = middle_of_block+3, x6=-2
19595 ld4r {v17.2d , v18.2d , v19.2d , v20.2d }, [x5], #32 with x5 = middle_of_block+3, x6=-5
19625 ld4r {v17.1d , v18.1d , v19.1d , v20.1d }, [x5], #32 with x5 = middle_of_block+3, x6=-4
[all …]
|
| /external/hyphenation-patterns/de/ |
| D | hyph-de-1996.pat.txt | 9873 ld4rü
|
| D | hyph-de-1901.pat.txt | 10030 ld4rü
|
| D | hyph-de-ch-1901.pat.txt | 9925 ld4rü
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.td | 4980 defm LD4R : SIMDLdR<1, 0b111, 0, "ld4r", "Four", 4, 8, 16, 32>;
|