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Searched refs:ldrh (Results 1 – 25 of 115) sorted by relevance

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/external/llvm/test/CodeGen/Thumb2/
Dthumb2-ldrh.ll6 ; CHECK: ldrh r0, [r0]
14 ; CHECK: ldrh.w r0, [r0, #2046]
24 ; CHECK: ldrh r0, [r0, r1]
33 ; CHECK: ldrh r0, [r0, #-128]
43 ; CHECK: ldrh r0, [r0, r1]
53 ; CHECK: ldrh.w r0, [r0, r1, lsl #2]
65 ; CHECK: ldrh r0, [r0, r1]
Dthumb2-ldr_ext.ll30 ; CHECK: ldrh
31 ; CHECK-NOT: ldrh
/external/libavc/common/armv8/
Dih264_padding_neon_av8.s355 ldrh w8, [x0]
358 ldrh w9, [x0]
362 ldrh w10, [x0]
368 ldrh w11, [x0]
384 ldrh w8, [x0]
387 ldrh w9, [x0]
391 ldrh w10, [x0]
397 ldrh w11, [x0]
413 ldrh w8, [x0]
416 ldrh w9, [x0]
[all …]
/external/llvm/test/CodeGen/ARM/
Dstruct_byval_arm_t1_t2.ll75 ;ARM: ldrh r{{[0-9]+}}, [{{.*}}], #2
77 ;THUMB2: ldrh r{{[0-9]+}}, [{{.*}}], #2
79 ;NO_NEON: ldrh r{{[0-9]+}}, [{{.*}}], #2
81 ;THUMB1: ldrh r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}}
84 ;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2
184 ;ARM: ldrh r{{[0-9]+}}, [{{.*}}], #2
187 ;THUMB2: ldrh r{{[0-9]+}}, [{{.*}}], #2
190 ;NO_NEON: ldrh r{{[0-9]+}}, [{{.*}}], #2
193 ;THUMB1: ldrh r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}}
197 ;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2
[all …]
Dfast-isel-ldrh-strh-arm.ll10 ; ARM: ldrh r0, [r0, #-16]
19 ; ARM: ldrh r0, [r0, #-32]
28 ; ARM: ldrh r0, [r0, #-254]
39 ; ARM: ldrh r0, [r0]
48 ; ARM: ldrh r0, [r0, #16]
57 ; ARM: ldrh r0, [r0, #32]
66 ; ARM: ldrh r0, [r0, #254]
76 ; ARM: ldrh r0, [r0]
Dfast-isel-fold.ll24 ; ARM: ldrh
27 ; THUMB: ldrh
53 ; ARM: ldrh
56 ; THUMB: ldrh
Dfast-isel-intrinsic.ll131 ; ARM: ldrh r1, [r0, #24]
142 ; THUMB: ldrh r1, [r0, #24]
156 ; ARM: ldrh r1, [r0, #16]
158 ; ARM: ldrh r1, [r0, #18]
160 ; ARM: ldrh r1, [r0, #20]
162 ; ARM: ldrh r1, [r0, #22]
164 ; ARM: ldrh r1, [r0, #24]
171 ; THUMB: ldrh r1, [r0, #16]
173 ; THUMB: ldrh r1, [r0, #18]
175 ; THUMB: ldrh r1, [r0, #20]
[all …]
Dfp16-promote.ll94 ; CHECK-ALL: ldrh {{r[0-9]+}}, [{{r[0-9]+}}]
154 ; CHECK-ALL: ldrh {{r[0-9]+}}, [{{r[0-9]+}}]
379 ; CHECK-ALL-NEXT: ldrh r0, [r0]
818 ; CHECK-ALL: ldrh
820 ; CHECK-ALL: ldrh
822 ; CHECK-ALL: ldrh
824 ; CHECK-ALL: ldrh
827 ; CHECK-ALL-DAG: ldrh
830 ; CHECK-ALL: ldrh
832 ; CHECK-ALL: ldrh
[all …]
Dbswap16.ll13 ; CHECK: ldrh r[[R1:[0-9]+]], [r0]
38 ; CHECK: ldrh r[[R0:[0-9]+]], [r0]
DMergeConsecutiveStores.ll6 ; CHECK: ldrh [[REG:r[0-9]+]], [{{.*}}]
38 ; CHECK: ldrh [[REG:r[0-9]+]], [{{.*}}]
70 ; CHECK-NOT: ldrh [[REG:r[0-9]+]], [{{.*}}]
Dload.ll41 ; CHECK-T1: ldrh r0, [r0, r1]
42 ; CHECK-T2: ldrh.w r0, [r0, r1, lsl #1]
110 ; CHECK-T1: ldrh r0, [r0]
130 ; CHECK: ldrh r0, [r0]
210 ; CHECK: ldrh r0, [r0, #62]
298 ; CHECK-T1: ldrh r0, [r0, r1]
299 ; CHECK-T2: ldrh.w r0, [r0, #64]
396 ; CHECK-T1: ldrh r0, [r0, r1]
397 ; CHECK-T2: ldrh.w r0, [r0, #4095]
503 ; CHECK: ldrh r0, [r0, r1]
Dfast-isel-ldr-str-arm.ll26 ; ARM: ldrh r{{[0-9]}}, [r0, #2]
35 ; ARM: ldrh.w r{{[0-9]}}, [r0, #126]
/external/libavc/common/arm/
Dih264_padding_neon.s311 ldrh r8, [r0], r1
312 ldrh r9, [r0], r1
314 ldrh r10, [r0], r1
318 ldrh r11, [r0], r1
332 ldrh r8, [r0], r1
333 ldrh r9, [r0], r1
335 ldrh r10, [r0], r1
339 ldrh r11, [r0], r1
353 ldrh r8, [r0], r1
354 ldrh r9, [r0], r1
[all …]
/external/llvm/test/CodeGen/AArch64/
Dfree-zext.ll6 ; CHECK: ldrh w[[B:[0-9]+]], [x1]
18 ; CHECK: ldrh w[[A:[0-9]+]], [x0]
35 ; CHECK: ldrh [[REG:w[0-9]+]]
41 ; CHECK: ldrh [[REG2:w[0-9]+]]
56 ; CHECK: ldrh [[REG:w[0-9]+]]
58 ; CHECK: ldrh [[REG:w[0-9]+]]
Darm64-strict-align.ll6 ; CHECK-STRICT: ldrh [[HIGH:w[0-9]+]], [x0, #2]
7 ; CHECK-STRICT: ldrh [[LOW:w[0-9]+]], [x0]
/external/llvm/test/CodeGen/Thumb/
Dcortex-m0-unaligned-access.ll6 ; V6M: ldrh
7 ; V6M: ldrh
9 ; V7M-NOT: ldrh
Dldr_ext.ll16 ; V5: ldrh
18 ; V6: ldrh
37 ; V5: ldrh
41 ; V6: ldrh
/external/libhevc/common/arm64/
Dihevc_padding.s219 ldrh w8,[x0]
221 ldrh w9,[x0]
223 ldrh w10,[x0]
225 ldrh w11,[x0]
465 ldrh w8,[x0, #-2]
467 ldrh w9,[x0, #-2]
469 ldrh w10,[x0, #-2]
471 ldrh w11,[x0, #-2]
/external/webrtc/webrtc/modules/audio_coding/codecs/isac/fix/source/
Dlattice_armv7.S44 ldrh r5, [r1] @ tmpAR = ar_f_Q0[n+1]
51 ldrh r7, [r3, #-2]! @ sth_Q15[k - 1]
52 ldrh r6, [r2, #-2]! @ cth_Q15[k - 1]
54 ldrh r8, [r0, #-2] @ ar_g_Q0[k - 1]
/external/libhevc/common/arm/
Dihevc_padding.s225 ldrh r8,[r0]
227 ldrh r9,[r0]
229 ldrh r10,[r0]
231 ldrh r11,[r0]
473 ldrh r8,[r0, #-2]
475 ldrh r9,[r0, #-2]
477 ldrh r10,[r0, #-2]
479 ldrh r11,[r0, #-2]
/external/llvm/test/MC/Disassembler/ARM/
Dmemory-arm-instructions.txt145 # CHECK: ldrh r3, [r4
146 # CHECK: ldrh r2, [r7, #4
147 # CHECK: ldrh r1, [r8, #64]!
148 # CHECK: ldrh r12, [sp], #4
164 # CHECK: ldrh r6, [r5, r4
165 # CHECK: ldrh r3, [r8, r11]!
166 # CHECK: ldrh r1, [r2, -r1]!
167 # CHECK: ldrh r9, [r7], r2
168 # CHECK: ldrh r4, [r3], -r2
Dthumb1.txt209 # CHECK: ldrh r3, [r3]
210 # CHECK: ldrh r4, [r6, #2]
211 # CHECK: ldrh r5, [r7, #62]
220 # CHECK: ldrh r6, [r2, r6]
/external/v8/test/cctest/
Dtest-disasm-arm.cc858 COMPARE(ldrh(r0, MemOperand(r1)), in TEST()
860 COMPARE(ldrh(r2, MemOperand(r3, 42)), in TEST()
862 COMPARE(ldrh(r4, MemOperand(r5, -42)), in TEST()
864 COMPARE(ldrh(r6, MemOperand(r7, 42, PostIndex)), in TEST()
866 COMPARE(ldrh(r8, MemOperand(r9, -42, PostIndex)), in TEST()
868 COMPARE(ldrh(r10, MemOperand(fp, 42, PreIndex)), in TEST()
870 COMPARE(ldrh(ip, MemOperand(sp, -42, PreIndex)), in TEST()
872 COMPARE(ldrh(r0, MemOperand(r1, r2)), in TEST()
874 COMPARE(ldrh(r0, MemOperand(r1, r2, NegOffset)), in TEST()
876 COMPARE(ldrh(r0, MemOperand(r1, r2, PostIndex)), in TEST()
[all …]
/external/llvm/test/MC/AArch64/
Darm64-elf-relocs.s130 ldrh w2, [x3, #:lo12:sym]
143 ldrh w23, [x29, #:dtprel_lo12_nc:sym]
156 ldrh w1, [x2, :tprel_lo12:sym]
/external/llvm/test/MC/ARM/
Dbasic-thumb-instructions.s323 ldrh r3, [r3]
324 ldrh r4, [r6, #2]
325 ldrh r5, [r7, #62]
327 @ CHECK: ldrh r3, [r3] @ encoding: [0x1b,0x88]
328 @ CHECK: ldrh r4, [r6, #2] @ encoding: [0x74,0x88]
329 @ CHECK: ldrh r5, [r7, #62] @ encoding: [0xfd,0x8f]
335 ldrh r6, [r2, r6]
337 @ CHECK: ldrh r6, [r2, r6] @ encoding: [0x96,0x5b]

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