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Searched refs:madd (Results 1 – 25 of 125) sorted by relevance

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/external/eigen/Eigen/src/Core/products/
DGeneralBlockPanelKernel.h206 …EIGEN_STRONG_INLINE void madd(const LhsPacket& a, const RhsPacket& b, AccPacket& c, AccPacket& tmp…
277 …EIGEN_STRONG_INLINE void madd(const LhsPacket& a, const RhsPacket& b, AccPacket& c, RhsPacket& tmp…
379 …EIGEN_STRONG_INLINE void madd(const LhsPacket& a, const RhsPacket& b, DoublePacket& c, RhsPacket& …
385 …EIGEN_STRONG_INLINE void madd(const LhsPacket& a, const RhsPacket& b, ResPacket& c, RhsPacket& /*t…
482 …EIGEN_STRONG_INLINE void madd(const LhsPacket& a, const RhsPacket& b, AccPacket& c, RhsPacket& tmp…
606 traits.madd(A0,B_0,C0,T0);
607 traits.madd(A1,B_0,C4,B_0);
609 traits.madd(A0,B_0,C1,T0);
610 traits.madd(A1,B_0,C5,B_0);
615 traits.madd(A0,B_0,C0,T0);
[all …]
/external/llvm/test/CodeGen/AArch64/
Dmadd-lohi.ll7 ; CHECK-DAG: madd [[PART1:x[0-9]+]], x0, x3, [[CARRY]]
8 ; CHECK: madd x1, x1, x2, [[PART1]]
13 ; CHECK-BE-DAG: madd [[PART1:x[0-9]+]], x1, x2, [[CARRY]]
14 ; CHECK-BE: madd x0, x0, x3, [[PART1]]
Dmul-lohi.ll21 ; The machine combiner should create madd instructions when
27 ; CHECK-NEXT: madd [[TEMP1:x[0-9]+]], x0, x3, [[HI]]
28 ; CHECK-NEXT: madd x1, x1, x2, [[TEMP1]]
39 ; CHECK-NEXT: madd [[TEMP1:x[0-9]+]], x0, x3, [[HI]]
40 ; CHECK-NEXT: madd x1, x1, x2, [[TEMP1]]
Daarch64-fix-cortex-a53-835769.ll33 ; CHECK-NEXT: madd
36 ; CHECK-NOWORKAROUND-NEXT: madd
39 ; CHECK-BASIC-PASS-DISABLED-NEXT: madd
51 ; CHECK-NEXT: madd
54 ; CHECK-NOWORKAROUND-NEXT: madd
312 ; CHECK-NEXT: madd
315 ; CHECK-NOWORKAROUND-NEXT: madd
328 ; CHECK-NEXT: madd
331 ; CHECK-NOWORKAROUND-NEXT: madd
409 ; CHECK-NEXT: madd
[all …]
Dfast-isel-gep.ll15 ; CHECK-NEXT: madd x0, x1, [[REG]], x0
46 ; CHECK-NEXT: madd {{x[0-9]+}}, [[REG1]], [[REG2]], x0
/external/llvm/test/MC/Mips/
Dmicromips-multiply-instructions.s12 # CHECK-EL: madd $4, $5 # encoding: [0xa4,0x00,0x3c,0xcb]
19 # CHECK-EB: madd $4, $5 # encoding: [0x00,0xa4,0xcb,0x3c]
23 madd $4, $5
Dmicromips-fpu-instructions.s66 # CHECK-EL: madd.s $f2, $f4, $f6, $f8 # encoding: [0x06,0x55,0x01,0x11]
67 # CHECK-EL: madd.d $f2, $f4, $f6, $f8 # encoding: [0x06,0x55,0x09,0x11]
131 # CHECK-EB: madd.s $f2, $f4, $f6, $f8 # encoding: [0x55,0x06,0x11,0x01]
132 # CHECK-EB: madd.d $f2, $f4, $f6, $f8 # encoding: [0x55,0x06,0x11,0x09]
192 madd.s $f2, $f4, $f6, $f8
193 madd.d $f2, $f4, $f6, $f8
Dmips64-alu-instructions.s78 # CHECK: madd $6, $7 # encoding: [0x00,0x00,0xc7,0x70]
103 madd $6,$7
Dmips-alu-instructions.s82 # CHECK: madd $6, $7 # encoding: [0x00,0x00,0xc7,0x70]
107 madd $6,$7
/external/llvm/test/CodeGen/Mips/
Dfmadd1.ll1 ; Check that madd.[ds], msub.[ds], nmadd.[ds], and nmsub.[ds] are supported
32 ; 32R2: madd.s $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
42 ; 64-DAG: madd.s $[[T0:f[0-9]+]], $f14, $f12, $f13
46 ; 64R2: madd.s $[[T0:f[0-9]+]], $f14, $f12, $f13
115 ; 32R2-NAN: madd.s $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
127 ; 64-NAN: madd.s $[[T0:f[0-9]+]], $f14, $f12, $f13
133 ; 64R2-NAN: madd.s $[[T0:f[0-9]+]], $f14, $f12, $f13
198 ; 32R2: madd.d $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
209 ; 64-DAG: madd.d $[[T0:f[0-9]+]], $f14, $f12, $f13
213 ; 64R2: madd.d $[[T0:f[0-9]+]], $f14, $f12, $f13
[all …]
Dinlineasm-cnstrnt-reg.ll37 ; CHECK-NEXT: madd ${{[0-9]+}}, ${{[0-9]+}}
41 …call i32 asm sideeffect "\09mtlo $3 \0A\09\09madd $1, $2 ", "=l,r,r,r"(i32 7, i32 6, i32 44) nounw…
/external/llvm/test/MC/Mips/mips32r6/
Dinvalid-mips32r2.s8 …madd.d $f18,$f19,$f26,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
9 …madd.s $f1,$f31,$f19,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
Dinvalid-mips32.s10 …madd $s6,$13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature …
11 …madd $zero,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature …
/external/llvm/test/MC/Mips/mips4/
Dinvalid-mips64.s15 …madd $s6,$t5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature no…
16 …madd $zero,$t1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature no…
Dinvalid-mips64r2.s18 …madd $s6,$t5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
19 …madd $zero,$t1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
/external/llvm/test/MC/Mips/mips5/
Dinvalid-mips64.s16 …madd $s6,$13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature no…
17 …madd $zero,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature no…
Dinvalid-mips64r2.s22 …madd $s6,$13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
23 …madd $zero,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
/external/llvm/test/MC/Mips/mips2/
Dinvalid-mips32r2.s23 …madd $s6,$t5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
24 …madd $zero,$t1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
25 …madd.d $f18,$f19,$f26,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
26 …madd.s $f1,$f31,$f19,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
/external/llvm/test/MC/Mips/dsp/
Dvalid.s49 …madd $ac1, $6, $7 # CHECK: madd $ac1, $6, $7 # encoding: [0x70,0x…
51 …madd $6, $7 # CHECK: madd $6, $7 # encoding: [0x70,0x…
/external/llvm/test/MC/Mips/mips32r3/
Dvalid.s100 madd $s6,$13
101 madd $zero,$9
102 madd.d $f18,$f19,$f26,$f20
103 madd.s $f1,$f31,$f19,$f25
/external/llvm/test/MC/Mips/mips32r2/
Dvalid.s100 madd $s6,$13
101 madd $zero,$9
102 madd.d $f18,$f19,$f26,$f20
103 madd.s $f1,$f31,$f19,$f25
/external/llvm/test/CodeGen/Mips/msa/
D3rf_4rf_q.ll17 %3 = tail call <8 x i16> @llvm.mips.madd.q.h(<8 x i16> %0, <8 x i16> %1, <8 x i16> %2)
22 declare <8 x i16> @llvm.mips.madd.q.h(<8 x i16>, <8 x i16>, <8 x i16>) nounwind
42 %3 = tail call <4 x i32> @llvm.mips.madd.q.w(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2)
47 declare <4 x i32> @llvm.mips.madd.q.w(<4 x i32>, <4 x i32>, <4 x i32>) nounwind
/external/llvm/test/MC/Mips/mips32r5/
Dvalid.s101 madd $s6,$13
102 madd $zero,$9
103 madd.d $f18,$f19,$f26,$f20
104 madd.s $f1,$f31,$f19,$f25
/external/libvorbis/
Dconfigure.ac177 CFLAGS="-O3 -Wall -Wextra -ffast-math -mfused-madd -D_REENTRANT"
178 PROFILE="-pg -g -O3 -ffast-math -mfused-madd -D_REENTRANT";;
181 CFLAGS="-O3 -Wall -Wextra -ffast-math -mfused-madd -mcpu=750 -D_REENTRANT"
182 PROFILE="-pg -g -O3 -ffast-math -mfused-madd -mcpu=750 -D_REENTRANT";;
/external/llvm/test/MC/Mips/mips32/
Dinvalid-mips32r2.s17 …madd.d $f18,$f19,$f26,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
18 …madd.s $f1,$f31,$f19,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…

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