Home
last modified time | relevance | path

Searched refs:memd (Results 1 – 21 of 21) sorted by relevance

/external/llvm/test/MC/Disassembler/Hexagon/
Dst.txt6 # CHECK: memd(r17 + r21<<#3) = r31:30
8 # CHECK: memd(#320) = r21:20
10 # CHECK: memd(##168) = r21:20
12 # CHECK: memd(r17+#168) = r21:20
14 # CHECK: memd(r17 ++ I:circ(m1)) = r21:20
16 # CHECK: memd(r17 ++ #40:circ(m1)) = r21:20
18 # CHECK: memd(r17++#40) = r21:20
20 # CHECK: memd(r17<<#3 + ##21) = r31:30
22 # CHECK: memd(r17++m1) = r21:20
24 # CHECK: memd(r17 ++ m1:brev) = r21:20
[all …]
Dld.txt6 # CHECK: r17:16 = memd(r21 + r31<<#3)
8 # CHECK: r17:16 = memd(#168)
10 # CHECK: r17:16 = memd(##168)
12 # CHECK: r17:16 = memd(r21 + #48)
14 # CHECK: r17:16 = memd(r21 ++ #40:circ(m1))
16 # CHECK: r17:16 = memd(r21 ++ I:circ(m1))
18 # CHECK: r17:16 = memd(r21 = ##31)
20 # CHECK: r17:16 = memd(r21++#40)
22 # CHECK: r17:16 = memd(r21++m1)
24 # CHECK: r17:16 = memd(r21 ++ m1:brev)
[all …]
/external/llvm/test/MC/Hexagon/
DasmMap.s56 #CHECK: 91dac00c { r13:12 = memd(r26{{ *}}+{{ *}}#0)
57 r13:12=memd(r26)
86 #CHECK: 41d0d804 { if (p3) r5:4 = memd(r16{{ *}}+{{ *}}#0)
87 if (p3) r5:4=memd(r16)
89 #CHECK: 45d9c00c { if (!p0) r13:12 = memd(r25{{ *}}+{{ *}}#0)
90 if (!p0) r13:12=memd(r25)
122 #CHECK: 40d9c601 { if (p1) memd(r25{{ *}}+{{ *}}#0) = r7:6
123 if (p1) memd(r25)=r7:6
125 #CHECK: 44dad803 { if (!p3) memd(r26{{ *}}+{{ *}}#0) = r25:24
126 if (!p3) memd(r26)=r25:24
[all …]
/external/llvm/test/CodeGen/Hexagon/
Dmem-fi-add.ll3 ; CHECK: memd(r29
4 ; CHECK: memd(r29
5 ; CHECK: memd(r29
6 ; CHECK: memd(r29
Dzextloadi1.ll5 ; CHECK: memd(##i129_s) = r{{[0-9]+:[0-9]+}}
8 ; CHECK: memd(##i65_s) = r{{[0-9]+:[0-9]+}}
Dsigned_immediates.ll28 ; CHECK: memd(r0++#-8) = r3:2
78 ; CHECK: memd(r0+#-8) = r3:2
Dsimpletailcall.ll4 ; CHECK-NOT: memd(r29
Dcirc_st.ll10 ; memd(r1++#-8:circ(m0)) = r1:0
44 ; CHECK: memd(r{{[0-9]*}}{{.}}++{{.}}#-8:circ(m{{[0-1]}}))
Dbrev_st.ll10 ; memd(r0++m0:brev) = r1:0
29 ; CHECK: memd(r{{[0-9]*}} ++ m{{[0-1]}}:brev)
Dabsaddr-store.ll45 ; CHECK: memd(##d){{ *}}={{ *}}r{{[0-9]+}}:{{[0-9]+}}
Dbrev_ld.ll11 ; r3:2 = memd(r0++m0:brev)
32 ; CHECK: memd(r{{[0-9]*}} ++ m{{[0-1]}}:brev)
Dcirc_ld.ll11 ; r3:2 = memd(r1++#-8:circ(m0))
48 ; CHECK: memd(r{{[0-9]*.}}++{{.}}#-8:circ(m{{[0-1]}}))
Dpostinc-offset.ll4 ; CHECK: ={{ *}}memd([[REG0:(r[0-9]+)]]{{ *}}++{{ *}}#8)
Didxload-with-zero-offset.ll64 ; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}memd(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}{{ *}}<<{{ *}}#…
Dearly-if.ll4 ; CHECK: if{{.*}}memd
/external/llvm/lib/Target/Hexagon/
DHexagonInstrAlias.td27 def : InstAlias<"memd({GP}+#$addr) = $Nt",
40 def : InstAlias<"$Nt = memd({GP}+#$addr)",
74 def : InstAlias<"memd($Rs) = $Rtt",
111 def : InstAlias<"$Rdd = memd($Rs)",
149 def : InstAlias<"if ($Pt) $Rdd = memd($Rs)",
166 def : InstAlias<"if ($Pt) memd($Rs) = $Rtt",
205 def : InstAlias<"if (!$Pt) $Rdd = memd($Rs)",
222 def : InstAlias<"if (!$Pt) memd($Rs) = $Rtt",
368 def : InstAlias<"if ($Pv.new) memd($Rs) = $Rtt",
384 def : InstAlias<"if (!$Pv.new) memd($Rs) = $Rtt",
[all …]
DHexagonInstrInfoV4.td437 def L4_loadrd_ap : T_LD_abs_set <"memd", DoubleRegs, 0b1110>;
495 def L4_loadrd_ur : T_LoadAbsReg<"memd", "LDrid", DoubleRegs, 0b1110>;
629 defm loadrd : ld_idxd_shl<"memd", "LDrid", DoubleRegs, 0b110>;
700 let isNVStorable = !if (!eq(mnemonic, "memd"), 0, !if(isHalf,0,1));
721 def S4_storerd_ap : T_ST_absset <"memd", "STrid", DoubleRegs,
774 let isNVStorable = !if (!eq(mnemonic, "memd"), 0, !if(isHalf,0,1));
794 def S4_storerd_ur : T_StoreAbsReg <"memd", "STrid", DoubleRegs, 0b110,
867 let isNVStorable = !if (!eq(mnemonic, "memd"), 0, !if(isH,0,1));
902 let isNVStorable = !if (!eq(mnemonic, "memd"), 0, !if(isH,0,1));
1032 defm storerd: ST_Idxd_shl<"memd", "STrid", DoubleRegs, 0b110>;
[all …]
DHexagonInstrInfo.td1723 defm loadrd: LD_Idxd <"memd", "LDrid", DoubleRegs, s11_3Ext, u6_3Ext, 0b1110>;
1920 defm loadrd : LD_PostInc <"memd", "LDrid", DoubleRegs, s4_3Imm, 0b1110>;
2004 def L2_loadrd_pr : T_load_pr <"memd", DoubleRegs, 0b1110, DoubleWordAccess>;
2070 def L2_loadrd_pcr : T_load_pcr <"memd", DoubleRegs, 0b1110>;
2156 def L2_loadrd_pci : T_load_pci <"memd", DoubleRegs, s4_3Imm, 0b1110>;
2178 def L2_loadrd_pci_pseudo : T_load_pci_pseudo <"memd", DoubleRegs>;
2274 def L2_loadrd_pbr : T_load_pbr <"memd", DoubleRegs, DoubleWordAccess, 0b1110>;
2298 def L2_loadrd_pbr_pseudo : T_load_pbr_pseudo <"memd", DoubleRegs>;
3386 defm storerd: ST_PostInc <"memd", "STrid", DoubleRegs, s4_3Imm, 0b1110>;
3416 let isNVStorable = !if(!eq(mnemonic,"memd"), 0, !if(isHalf,0,1));
[all …]
DHexagonIsetDx.td456 "$Rdd = memd(r29 + #$u5_3)"> {
512 "memd(r29 + #$s6_3) = $Rtt"> {
DHexagonInstrFormats.td61 def DoubleWordAccess : MemAccessSize<4>;// Double word access instruction (memd)
/external/valgrind/VEX/test/
Dmmxtest.c137 #define mmx_m2m(op, mems, memd) \ argument
142 mmx_trace = (memd); \
143 fprintf(stderr, #memd "=0x%016llx) => ", mmx_trace.q); \
147 : "=X" (memd) \
149 mmx_trace = (memd); \
150 fprintf(stderr, #memd "=0x%016llx\n", mmx_trace.q); \
171 #define mmx_m2m(op, mems, memd) \ argument
175 : "=X" (memd) \