| /external/llvm/test/MC/PowerPC/ |
| D | ppc64-encoding-bookIII.s | 24 # CHECK-BE: mfspr 4, 260 # encoding: [0x7c,0x84,0x42,0xa6]
25 # CHECK-LE: mfspr 4, 260 # encoding: [0xa6,0x42,0x84,0x7c]
28 # CHECK-BE: mfspr 4, 261 # encoding: [0x7c,0x85,0x42,0xa6]
29 # CHECK-LE: mfspr 4, 261 # encoding: [0xa6,0x42,0x85,0x7c]
32 # CHECK-BE: mfspr 4, 262 # encoding: [0x7c,0x86,0x42,0xa6]
33 # CHECK-LE: mfspr 4, 262 # encoding: [0xa6,0x42,0x86,0x7c]
36 # CHECK-BE: mfspr 4, 263 # encoding: [0x7c,0x87,0x42,0xa6]
37 # CHECK-LE: mfspr 4, 263 # encoding: [0xa6,0x42,0x87,0x7c]
40 # CHECK-BE: mfspr 2, 260 # encoding: [0x7c,0x44,0x42,0xa6]
41 # CHECK-LE: mfspr 2, 260 # encoding: [0xa6,0x42,0x44,0x7c]
[all …]
|
| D | deprecated-p7.s | 7 # CHECK: mfspr 3, 268
|
| D | ppc64-encoding-ext.s | 3449 # CHECK-BE: mfspr 2, 22 # encoding: [0x7c,0x56,0x02,0xa6]
3450 # CHECK-LE: mfspr 2, 22 # encoding: [0xa6,0x02,0x56,0x7c]
3455 # CHECK-BE: mfspr 2, 25 # encoding: [0x7c,0x59,0x02,0xa6]
3456 # CHECK-LE: mfspr 2, 25 # encoding: [0xa6,0x02,0x59,0x7c]
3461 # CHECK-BE: mfspr 2, 26 # encoding: [0x7c,0x5a,0x02,0xa6]
3462 # CHECK-LE: mfspr 2, 26 # encoding: [0xa6,0x02,0x5a,0x7c]
3467 # CHECK-BE: mfspr 2, 27 # encoding: [0x7c,0x5b,0x02,0xa6]
3468 # CHECK-LE: mfspr 2, 27 # encoding: [0xa6,0x02,0x5b,0x7c]
3534 # CHECK-BE: mfspr 4, 272 # encoding: [0x7c,0x90,0x42,0xa6]
3535 # CHECK-LE: mfspr 4, 272 # encoding: [0xa6,0x42,0x90,0x7c]
[all …]
|
| D | ppc64-encoding.s | 821 # CHECK-BE: mfspr 2, 600 # encoding: [0x7c,0x58,0x92,0xa6]
822 # CHECK-LE: mfspr 2, 600 # encoding: [0xa6,0x92,0x58,0x7c]
823 mfspr 2, 600
|
| /external/fio/arch/ |
| D | arch-ppc.h | 51 static inline unsigned int mfspr(unsigned int reg) in mfspr() function
71 tbu0 = mfspr(SPRN_ATBU); in get_cpu_clock()
72 tbl = mfspr(SPRN_ATBL); in get_cpu_clock()
73 tbu1 = mfspr(SPRN_ATBU); in get_cpu_clock()
75 tbu0 = mfspr(SPRN_TBRU); in get_cpu_clock()
76 tbl = mfspr(SPRN_TBRL); in get_cpu_clock()
77 tbu1 = mfspr(SPRN_TBRU); in get_cpu_clock()
|
| /external/llvm/test/MC/Disassembler/PowerPC/ |
| D | ppc64-encoding-bookIII.txt | 18 # CHECK: mfspr 4, 272
21 # CHECK: mfspr 4, 273
24 # CHECK: mfspr 4, 274
27 # CHECK: mfspr 4, 275
57 # CHECK: mfspr 4, 22
66 # CHECK: mfspr 4, 25
72 # CHECK: mfspr 4, 26
78 # CHECK: mfspr 4, 27
|
| D | ppc64-encoding.txt | 646 # CHECK: mfspr 2, 600
|
| D | ppc64le-encoding.txt | 646 # CHECK: mfspr 2, 600
|
| /external/llvm/test/CodeGen/PowerPC/ |
| D | ppc32-cyclecounter.ll | 13 ; CHECK: mfspr 3, 269
14 ; CHECK: mfspr 4, 268
15 ; CHECK: mfspr [[REG:[0-9]+]], 269
|
| D | mftb.ll | 3 ; On all other CPUs (including generic, ppc, ppc64), the mfspr instruction
29 ; CHECK-MFSPR: mfspr 3, 268
41 ; CHECK-MFSPR: mfspr 3, 269
53 ; CHECK-MFSPR: mfspr 3, 268
65 ; CHECK-MFSPR: mfspr 3, 269
|
| D | htm.ll | 91 ; CHECK: mfspr [[REG1:[0-9]+]], 130
99 ; CHECK: mfspr [[REG1:[0-9]+]], 131
107 ; CHECK: mfspr [[REG1:[0-9]+]], 128
115 ; CHECK: mfspr [[REG1:[0-9]+]], 129
|
| D | ppc64-cyclecounter.ll | 12 ; CHECK: mfspr 3, 268
|
| D | novrsave.ll | 14 ; CHECK-NOT: mfspr
|
| D | vrsave-spill.ll | 13 ; CHECK: mfspr r{{[0-9]+}}, 256
|
| D | sjlj.ll | 66 ; CHECK-NOT: mfspr
|
| /external/valgrind/coregrind/m_dispatch/ |
| D | dispatch-ppc32-linux.S | 140 mfspr 6,256 /* vrsave reg is spr number 256 */
337 mfspr 4,256 /* VRSAVE reg is spr number 256 */
|
| D | dispatch-ppc64be-linux.S | 155 mfspr 6,256 /* vrsave reg is spr number 256 */
306 mfspr 5,256 /* VRSAVE reg is spr number 256 */
|
| D | dispatch-ppc64le-linux.S | 176 mfspr 6,256 /* vrsave reg is spr number 256 */
332 mfspr 5,256 /* VRSAVE reg is spr number 256 */
|
| /external/compiler-rt/lib/tsan/rtl/ |
| D | tsan_rtl_ppc64.S | 102 mfspr r0,256
247 mfspr r0,256
|
| /external/valgrind/none/tests/ppc32/ |
| D | jm-int.stdout.exp | 1181 mfspr 1 (00000000) -> mtxer -> mfxer => 00000000
1182 mfspr 1 (000f423f) -> mtxer -> mfxer => 0000003f
1183 mfspr 1 (ffffffff) -> mtxer -> mfxer => e000007f
1184 mfspr 8 (00000000) -> mtlr -> mflr => 00000000
1185 mfspr 8 (000f423f) -> mtlr -> mflr => 000f423f
1186 mfspr 8 (ffffffff) -> mtlr -> mflr => ffffffff
1187 mfspr 9 (00000000) -> mtctr -> mfctr => 00000000
1188 mfspr 9 (000f423f) -> mtctr -> mfctr => 000f423f
1189 mfspr 9 (ffffffff) -> mtctr -> mfctr => ffffffff
|
| /external/llvm/lib/Target/PowerPC/ |
| D | README_ALTIVEC.txt | 123 mfspr r2, 256
152 mfspr r2, 256
|
| D | PPCInstr64Bit.td | 334 "mfspr $RT, $SPR", IIC_SprMFSPR>;
361 "mfspr $rT, 268", IIC_SprMFTB>,
363 // Note that encoding mftb using mfspr is now the preferred form,
365 // now been phased out. Using mfspr, however, is known not to work on
|
| /external/libunwind_llvm/src/ |
| D | UnwindRegistersSave.S | 135 mfspr r0,256
|
| /external/valgrind/none/tests/ppc64/ |
| D | jm-int.stdout.exp-LE | 1457 mfspr 1 (00000000) -> mtxer -> mfxer => 0000000000000000
1458 mfspr 1 (be991def) -> mtxer -> mfxer => 00000000a000006f
1459 mfspr 1 (ffffffff) -> mtxer -> mfxer => 00000000e000007f
1460 mfspr 8 (00000000) -> mtlr -> mflr => 0000000000000000
1461 mfspr 8 (be991def) -> mtlr -> mflr => ffffffffbe991def
1462 mfspr 8 (ffffffff) -> mtlr -> mflr => ffffffffffffffff
1463 mfspr 9 (00000000) -> mtctr -> mfctr => 0000000000000000
1464 mfspr 9 (be991def) -> mtctr -> mfctr => ffffffffbe991def
1465 mfspr 9 (ffffffff) -> mtctr -> mfctr => ffffffffffffffff
|
| /external/valgrind/docs/internals/ |
| D | 3_3_BUGSTATUS.txt | 33 dis_proc_ctl(ppc)(mfspr,SPR)(0x11F)
|