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Searched refs:no_shift (Results 1 – 10 of 10) sorted by relevance

/external/llvm/lib/Target/ARM/
DARMFastISel.cpp2635 /* 1 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift, 31 }, in ARMEmitIntExt()
2636 /* 1 bit zext */ { ARM::tLSRri , 0, ARM_AM::no_shift, 31 } }, in ARMEmitIntExt()
2637 /* 8 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift, 24 }, in ARMEmitIntExt()
2638 /* 8 bit zext */ { ARM::tLSRri , 0, ARM_AM::no_shift, 24 } }, in ARMEmitIntExt()
2639 /* 16 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift, 16 }, in ARMEmitIntExt()
2640 /* 16 bit zext */ { ARM::tLSRri , 0, ARM_AM::no_shift, 16 } } in ARMEmitIntExt()
2645 /* 1 bit sext */ { { ARM::KILL , 0, ARM_AM::no_shift, 0 }, in ARMEmitIntExt()
2646 /* 1 bit zext */ { ARM::ANDri , 1, ARM_AM::no_shift, 1 } }, in ARMEmitIntExt()
2647 /* 8 bit sext */ { { ARM::SXTB , 0, ARM_AM::no_shift, 0 }, in ARMEmitIntExt()
2648 /* 8 bit zext */ { ARM::ANDri , 1, ARM_AM::no_shift, 255 } }, in ARMEmitIntExt()
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DARMSelectionDAGInfo.h25 default: return ARM_AM::no_shift; in getShiftOpcForNode()
DARMISelDAGToDAG.cpp567 if (ShOpcVal == ARM_AM::no_shift) return false; in SelectImmShifterOperand()
591 if (ShOpcVal == ARM_AM::no_shift) return false; in SelectRegShifterOperand()
706 if (ShOpcVal != ARM_AM::no_shift) { in SelectLdStSOReg()
716 ShOpcVal = ARM_AM::no_shift; in SelectLdStSOReg()
719 ShOpcVal = ARM_AM::no_shift; in SelectLdStSOReg()
724 if (N.getOpcode() != ISD::SUB && ShOpcVal == ARM_AM::no_shift && in SelectLdStSOReg()
728 if (ShOpcVal != ARM_AM::no_shift) { in SelectLdStSOReg()
739 ShOpcVal = ARM_AM::no_shift; in SelectLdStSOReg()
742 ShOpcVal = ARM_AM::no_shift; in SelectLdStSOReg()
809 ARM_AM::no_shift), in SelectAddrMode2Worker()
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DARMLoadStoreOptimizer.cpp1340 int Imm = ARM_AM::getAM2Opc(AddSub, Bytes, ARM_AM::no_shift); in MergeBaseUpdateLoadStore()
1357 int Imm = ARM_AM::getAM2Opc(AddSub, Bytes, ARM_AM::no_shift); in MergeBaseUpdateLoadStore()
DARMFrameLowering.cpp1047 MIB.addImm(ARM_AM::getAM2Opc(ARM_AM::add, 4, ARM_AM::no_shift)); in emitPopInst()
DARMISelLowering.cpp11027 if (ShOpcVal != ARM_AM::no_shift) { in getARMIndexedAddressParts()
/external/llvm/lib/Target/ARM/MCTargetDesc/
DARMAddressingModes.h28 no_shift = 0, enumerator
DARMMCCodeEmitter.cpp207 case ARM_AM::no_shift: in getShiftOp()
/external/llvm/lib/Target/ARM/AsmParser/
DARMAsmParser.cpp1042 return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift; in isPostIdxReg()
1149 if (Memory.ShiftType != ARM_AM::no_shift) return false; in isAddrMode3()
1163 return PostIdxReg.ShiftTy == ARM_AM::no_shift; in isAM3Offset()
1188 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0) in isMemTBB()
1209 if (Memory.ShiftType == ARM_AM::no_shift) in isT2MemRegOffset()
1219 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0) in isMemThumbRR()
2049 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift); in addAddrMode2Operands()
2070 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift); in addAM2OffsetImmOperands()
2813 if (PostIdxReg.ShiftTy != ARM_AM::no_shift) in print()
2986 .Default(ARM_AM::no_shift); in tryParseShiftRegister()
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/external/llvm/lib/Target/ARM/InstPrinter/
DARMInstPrinter.cpp44 if (ShOpc == ARM_AM::no_shift || (ShOpc == ARM_AM::lsl && !ShImm)) in printRegImmShift()