Searched refs:noreg (Results 1 – 9 of 9) sorted by relevance
| /external/llvm/test/CodeGen/ARM/ |
| D | subreg-remat.ll | 8 ; %vreg6:ssub_0<def> = VLDRS <cp#0>, 0, pred:14, pred:%noreg; mem:LD4[ConstantPool] DPR_VFP2:%vre…
34 ; %vreg2:ssub_0<def> = VLDRS <cp#0>, 0, pred:14, pred:%noreg, %vreg2<imp-def>; mem:LD4[ConstantPo…
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| D | 2014-01-09-pseudo_expand_implicit_reg.ll | 7 ; CHECK: VST1d64Q %R{{[0-9]+}}<kill>, 8, %D{{[0-9]+}}, pred:14, pred:%noreg, %Q{{[0-9]+}}_Q{{[0-9]+…
40 ; CHECK: VTBX4 {{.*}}, pred:14, pred:%noreg, %Q{{[0-9]+}}_Q{{[0-9]+}}<imp-use>
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| D | 2011-11-14-EarlyClobber.ll | 12 ; %vreg12<earlyclobber,def> = t2STR_PRE %vreg6, %vreg12, 32, pred:14, pred:%noreg
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| /external/llvm/test/CodeGen/MIR/X86/ |
| D | null-register-operands.mir | 20 %eax = MOV32rm %rdi, 1, _, 0, %noreg
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| /external/llvm/test/CodeGen/MIR/ARM/ |
| D | sched-it-debug-nodes.mir | 36 ; CHECK: * DBG_VALUE %R1, %noreg, !"u"
37 ; CHECK-NOT: * DBG_VALUE %R1<kill>, %noreg, !"u"
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| /external/llvm/test/CodeGen/X86/ |
| D | inline-asm-fpstack.ll | 350 …$0> [sideeffect] [mayload] [attdialect], $0:[mem], %EAX<undef>, 1, %noreg, 0, %noreg, $1:[clobber]…
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| /external/llvm/docs/ |
| D | MIRLangRef.rst | 350 represented using a '``%noreg``' named register, although the former syntax
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| /external/v8/test/cctest/ |
| D | test-assembler-arm64.cc | 9684 TEST(noreg) { in TEST() argument
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| /external/vixl/test/ |
| D | test-assembler-a64.cc | 14010 TEST(noreg) { in TEST() argument
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