| /external/llvm/test/MC/Mips/micromips-dsp/ |
| D | valid.s | 16 dpau.h.qbr $ac2, $20, $21 # CHECK: dpau.h.qbr $ac2, $20, $21 # encoding: [0x02,0xb4,0xb0,0xbc]
43 precequ.ph.qbr $9, $10 # CHECK: precequ.ph.qbr $9, $10 # encoding: [0x01,0x2a,0x91,0x3c]
47 preceu.ph.qbr $17, $18 # CHECK: preceu.ph.qbr $17, $18 # encoding: [0x02,0x32,0xd1,0x3c]
79 dpsu.h.qbr $ac1, $4, $6 # CHECK: dpsu.h.qbr $ac1, $4, $6 # encoding: [0x00,0xc4,0x74,0xbc]
83 muleu_s.ph.qbr $1, $2, $3 # CHECK: muleu_s.ph.qbr $1, $2, $3 # encoding: [0x00,0x62,0x08,0xd5]
|
| /external/llvm/test/MC/Mips/dsp/ |
| D | valid.s | 28 …dpau.h.qbr $ac1, $11, $12 # CHECK: dpau.h.qbr $ac1, $11, $12 # encoding: [0x7d,0x…
32 …dpsu.h.qbr $ac1, $7, $8 # CHECK: dpsu.h.qbr $ac1, $7, $8 # encoding: [0x7c,0x…
74 …muleu_s.ph.qbr $fp, $ra, $1 # CHECK: muleu_s.ph.qbr $fp, $ra, $1 # encoding: [0x7f,0x…
88 …precequ.ph.qbr $23, $24 # CHECK: precequ.ph.qbr $23, $24 # encoding: [0x7c,0x…
92 …preceu.ph.qbr $27, $gp # CHECK: preceu.ph.qbr $27, $gp # encoding: [0x7c,0x…
|
| /external/llvm/test/MC/Mips/micromips-dspr2/ |
| D | valid.s | 28 dpau.h.qbr $ac2, $20, $21 # CHECK: dpau.h.qbr $ac2, $20, $21 # encoding: [0x02,0xb4,0xb0,0xbc]
56 precequ.ph.qbr $9, $10 # CHECK: precequ.ph.qbr $9, $10 # encoding: [0x01,0x2a,0x91,0x3c]
60 preceu.ph.qbr $17, $18 # CHECK: preceu.ph.qbr $17, $18 # encoding: [0x02,0x32,0xd1,0x3c]
109 dpsu.h.qbr $ac1, $4, $6 # CHECK: dpsu.h.qbr $ac1, $4, $6 # encoding: [0x00,0xc4,0x74,0xbc]
122 muleu_s.ph.qbr $1, $2, $3 # CHECK: muleu_s.ph.qbr $1, $2, $3 # encoding: [0x00,0x62,0x08,0xd5]
|
| /external/llvm/test/MC/Mips/dspr2/ |
| D | valid.s | 45 …dpau.h.qbr $ac1, $11, $12 # CHECK: dpau.h.qbr $ac1, $11, $12 # encoding: [0x7d,0x6c,0…
53 …dpsu.h.qbr $ac1, $7, $8 # CHECK: dpsu.h.qbr $ac1, $7, $8 # encoding: [0x7c,0xe8,0…
98 …muleu_s.ph.qbr $fp, $ra, $1 # CHECK: muleu_s.ph.qbr $fp, $ra, $1 # encoding: [0x7f,0xe1,0…
116 …precequ.ph.qbr $23,$24 # CHECK: precequ.ph.qbr $23, $24 # encoding: [0x7c,0x18,0…
120 …preceu.ph.qbr $27,$28 # CHECK: preceu.ph.qbr $27, $gp # encoding: [0x7c,0x1c,0…
|
| /external/llvm/test/MC/Disassembler/Mips/micromips-dsp/ |
| D | valid.txt | 15 0x02 0xb4 0xb0 0xbc # CHECK: dpau.h.qbr $ac2, $20, $21
42 0x01 0x2a 0x91 0x3c # CHECK: precequ.ph.qbr $9, $10
46 0x02 0x32 0xd1 0x3c # CHECK: preceu.ph.qbr $17, $18
78 0x00 0xc4 0x74 0xbc # CHECK: dpsu.h.qbr $ac1, $4, $6
82 0x00 0x62 0x08 0xd5 # CHECK: muleu_s.ph.qbr $1, $2, $3
|
| /external/llvm/test/MC/Disassembler/Mips/micromips-dspr2/ |
| D | valid.txt | 27 0x02 0xb4 0xb0 0xbc # CHECK: dpau.h.qbr $ac2, $20, $21
55 0x01 0x2a 0x91 0x3c # CHECK: precequ.ph.qbr $9, $10
59 0x02 0x32 0xd1 0x3c # CHECK: preceu.ph.qbr $17, $18
108 0x00 0xc4 0x74 0xbc # CHECK: dpsu.h.qbr $ac1, $4, $6
121 0x00 0x62 0x08 0xd5 # CHECK: muleu_s.ph.qbr $1, $2, $3
|
| /external/llvm/test/MC/Disassembler/Mips/dsp/ |
| D | valid.txt | 26 0x7d 0x6c 0x09 0xf0 # CHECK: dpau.h.qbr $ac1, $11, $12
30 0x7c 0xe8 0x0b 0xf0 # CHECK: dpsu.h.qbr $ac1, $7, $8
72 0x7f 0xe1 0xf1 0xd0 # CHECK: muleu_s.ph.qbr $fp, $ra, $1
86 0x7c 0x18 0xb9 0x52 # CHECK: precequ.ph.qbr $23, $24
90 0x7c 0x1c 0xdf 0x52 # CHECK: preceu.ph.qbr $27, $gp
|
| /external/valgrind/none/tests/mips32/ |
| D | mips32_dsp.stdout.exp-BE | 892 dpau.h.qbr $ac3, $t4, $t5 :: rs 0x00000000 rt 0x00000000 inHI 0xffffffff inLO 0x80000000 outHI 0xff…
893 dpau.h.qbr $ac0, $t0, $t1 :: rs 0x00000004 rt 0x40000000 inHI 0x00000000 inLO 0x00000006 outHI 0x00…
894 dpau.h.qbr $ac1, $t2, $t3 :: rs 0x80002435 rt 0x80003421 inHI 0x00000000 inLO 0x40000000 outHI 0x00…
895 dpau.h.qbr $ac3, $t6, $t7 :: rs 0x76548000 rt 0x73468000 inHI 0x00000000 inLO 0x7fffffff outHI 0x00…
896 dpau.h.qbr $ac0, $t5, $t3 :: rs 0x80000000 rt 0x80000000 inHI 0x00000000 inLO 0x00000001 outHI 0x00…
897 dpau.h.qbr $ac1, $t2, $t4 :: rs 0x00010001 rt 0xffffffff inHI 0xffffffff inLO 0xffffffff outHI 0x00…
898 dpau.h.qbr $ac2, $t0, $t8 :: rs 0x7fff7fff rt 0x7fff7fff inHI 0xffffffff inLO 0xffffffff outHI 0x00…
899 dpau.h.qbr $ac0, $t0, $t1 :: rs 0x0000c420 rt 0x00000555 inHI 0x00000000 inLO 0x0fde3126 outHI 0x00…
900 dpau.h.qbr $ac1, $t2, $t3 :: rs 0x00000000 rt 0x00000000 inHI 0x00000000 inLO 0x55555555 outHI 0x00…
901 dpau.h.qbr $ac2, $t4, $t1 :: rs 0x80000000 rt 0x80000000 inHI 0xffffffff inLO 0xffff2435 outHI 0xff…
[all …]
|
| D | mips32_dsp.stdout.exp-LE | 892 dpau.h.qbr $ac3, $t4, $t5 :: rs 0x00000000 rt 0x00000000 inHI 0xffffffff inLO 0x80000000 outHI 0xff…
893 dpau.h.qbr $ac0, $t0, $t1 :: rs 0x00000004 rt 0x40000000 inHI 0x00000000 inLO 0x00000006 outHI 0x00…
894 dpau.h.qbr $ac1, $t2, $t3 :: rs 0x80002435 rt 0x80003421 inHI 0x00000000 inLO 0x40000000 outHI 0x00…
895 dpau.h.qbr $ac3, $t6, $t7 :: rs 0x76548000 rt 0x73468000 inHI 0x00000000 inLO 0x7fffffff outHI 0x00…
896 dpau.h.qbr $ac0, $t5, $t3 :: rs 0x80000000 rt 0x80000000 inHI 0x00000000 inLO 0x00000001 outHI 0x00…
897 dpau.h.qbr $ac1, $t2, $t4 :: rs 0x00010001 rt 0xffffffff inHI 0xffffffff inLO 0xffffffff outHI 0x00…
898 dpau.h.qbr $ac2, $t0, $t8 :: rs 0x7fff7fff rt 0x7fff7fff inHI 0xffffffff inLO 0xffffffff outHI 0x00…
899 dpau.h.qbr $ac0, $t0, $t1 :: rs 0x0000c420 rt 0x00000555 inHI 0x00000000 inLO 0x0fde3126 outHI 0x00…
900 dpau.h.qbr $ac1, $t2, $t3 :: rs 0x00000000 rt 0x00000000 inHI 0x00000000 inLO 0x55555555 outHI 0x00…
901 dpau.h.qbr $ac2, $t4, $t1 :: rs 0x80000000 rt 0x80000000 inHI 0xffffffff inLO 0xffff2435 outHI 0xff…
[all …]
|
| /external/llvm/test/MC/Disassembler/Mips/dspr2/ |
| D | valid.txt | 43 0x7d 0x6c 0x09 0xf0 # CHECK: dpau.h.qbr $ac1, $11, $12
51 0x7c 0xe8 0x0b 0xf0 # CHECK: dpsu.h.qbr $ac1, $7, $8
96 0x7f 0xe1 0xf1 0xd0 # CHECK: muleu_s.ph.qbr $fp, $ra, $1
114 0x7c 0x18 0xb9 0x52 # CHECK: precequ.ph.qbr $23, $24
118 0x7c 0x1c 0xdf 0x52 # CHECK: preceu.ph.qbr $27, $gp
|
| /external/llvm/test/MC/Mips/mips32r2/ |
| D | invalid-dsp.s | 29 …dpau.h.qbr $ac1,$s7,$s6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
33 …dpsu.h.qbr $ac2,$a1,$s6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
59 …muleu_s.ph.qbr $a1,$ra,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
69 …precequ.ph.qbr $ra,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
73 …preceu.ph.qbr $gp,$s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
|
| D | invalid-dspr2.s | 42 …dpau.h.qbr $ac1,$s7,$s6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f…
50 …dpsu.h.qbr $ac2,$a1,$s6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f…
80 …muleu_s.ph.qbr $a1,$ra,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f…
94 …precequ.ph.qbr $ra,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f…
98 …preceu.ph.qbr $gp,$s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f…
|
| /external/llvm/test/CodeGen/Mips/ |
| D | dsp-r1.ll | 125 ; CHECK: dpau.h.qbr
129 %3 = tail call i64 @llvm.mips.dpau.h.qbr(i64 %a0, <4 x i8> %1, <4 x i8> %2)
133 declare i64 @llvm.mips.dpau.h.qbr(i64, <4 x i8>, <4 x i8>) nounwind readnone
149 ; CHECK: dpsu.h.qbr
153 %3 = tail call i64 @llvm.mips.dpsu.h.qbr(i64 %a0, <4 x i8> %1, <4 x i8> %2)
157 declare i64 @llvm.mips.dpsu.h.qbr(i64, <4 x i8>, <4 x i8>) nounwind readnone
550 ; CHECK: muleu_s.ph.qbr
554 %2 = tail call <2 x i16> @llvm.mips.muleu.s.ph.qbr(<4 x i8> %0, <2 x i16> %1)
560 declare <2 x i16> @llvm.mips.muleu.s.ph.qbr(<4 x i8>, <2 x i16>) nounwind
1053 ; CHECK: precequ.ph.qbr
[all …]
|
| /external/llvm/lib/Target/Mips/ |
| D | MicroMipsDSPInstrInfo.td | 36 class DPAU_H_QBR_MM_ENC : POOL32A_2RAC_FMT<"dpau.h.qbr", 0b11000010>;
74 class PRECEQU_PH_QBR_MM_ENC : POOL32A_2R_FMT<"precequ.ph.qbr", 0b1001000100>;
78 class PRECEU_PH_QBR_MM_ENC : POOL32A_2R_FMT<"preceu.ph.qbr", 0b1101000100>;
111 class DPSU_H_QBR_MM_ENC : POOL32A_2RAC_FMT<"dpsu.h.qbr", 0b11010010>;
118 class MULEU_S_PH_QBR_MM_ENC : POOL32A_3RB0_FMT<"muleu_s.ph.qbr", 0b0011010101>;
184 "precequ.ph.qbr", int_mips_precequ_ph_qbr, NoItinerary, DSPROpnd>;
192 "preceu.ph.qbr", int_mips_preceu_ph_qbr, NoItinerary, DSPROpnd>;
|
| D | MipsDSPInstrInfo.td | 638 class PRECEQU_PH_QBR_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbr",
654 class PRECEU_PH_QBR_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbr",
733 class MULEU_S_PH_QBR_DESC : ADDU_QB_DESC_BASE<"muleu_s.ph.qbr",
777 class DPAU_H_QBR_DESC : DPA_W_PH_DESC_BASE<"dpau.h.qbr", MipsDPAU_H_QBR>;
781 class DPSU_H_QBR_DESC : DPA_W_PH_DESC_BASE<"dpsu.h.qbr", MipsDPSU_H_QBR>;
|
| /external/libjpeg-turbo/simd/ |
| D | jsimd_mips_dspr2.S | 926 preceu.ph.qbr t0, t0 // t0 = 0|A3|0|A2
927 preceu.ph.qbr t2, t2 // t2 = 0|B3|0|B2
1040 preceu.ph.qbr t0, t0 // t0 = |0|P1|0|P0|
1041 preceu.ph.qbr t2, t2 // t2 = |0|P5|0|P4|
1043 preceu.ph.qbr t1, t1 // t1 = |0|P2|0|P1|
3990 preceu.ph.qbr t3, t1
3993 preceu.ph.qbr t5, t2
4004 preceu.ph.qbr t3, t1
4010 preceu.ph.qbr t5, t2
4021 preceu.ph.qbr t3, t1
[all …]
|
| /external/aac/libAACenc/src/ |
| D | adj_thr.cpp | 2130 INT qmin, qbr, qbres, qmbr; in FDKaacEnc_bitresCalcBitFac() local
2173 bits_ratio = fDivNorm(bitresBits, avgBits, &qbr); in FDKaacEnc_bitresCalcBitFac()
2174 qbr = DFRACT_BITS-1-qbr; in FDKaacEnc_bitresCalcBitFac()
2178 qmin = fixMin(qbr, (DFRACT_BITS-1)); in FDKaacEnc_bitresCalcBitFac()
2179 bits_ratio = bits_ratio >> (qbr - qmin); in FDKaacEnc_bitresCalcBitFac()
|
| /external/svox/pico_resources/tools/LingwareBuilding/PicoLingware_source_files/textana/en-US/ |
| D | en-US_lexpos.utf | 2673 N "laboratories" "l'qbr@tO:ri:z"
|
| /external/chromium-trace/catapult/tracing/test_data/ |
| D | ddms_calculator_start.trace | 15398 �Qqbr��`��
192452 �m�qbr
351326 � qbr�Sg��
365310 �qbr����
438749 I� qbr��� ��
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|