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Searched refs:r25 (Results 1 – 25 of 41) sorted by relevance

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/external/llvm/test/MC/Hexagon/
DasmMap.s17 #CHECK: 4519d817 { if (!p3) r23 = memb(r25{{ *}}+{{ *}}#0)
18 if (!p3) r23=memb(r25)
44 #CHECK: 90e2c018 { r25:24 = membh(r2{{ *}}+{{ *}}#0)
45 r25:24=membh(r2)
77 #CHECK: 4449d900 { if (!p0) memh(r9{{ *}}+{{ *}}#0) = r25
78 if (!p0) memh(r9)=r25
89 #CHECK: 45d9c00c { if (!p0) r13:12 = memd(r25{{ *}}+{{ *}}#0)
90 if (!p0) r13:12=memd(r25)
122 #CHECK: 40d9c601 { if (p1) memd(r25{{ *}}+{{ *}}#0) = r7:6
123 if (p1) memd(r25)=r7:6
[all …]
Dv60-shift.s8 #CHECK: 1999d645 { v5.uh = vlsr(v22.uh,{{ *}}r25) }
9 v5.uh=vlsr(v22.uh,r25)
Dv60-vmpy1.s5 #CHECK: 1939c223 { v3.w = vdmpy(v3:2.h,{{ *}}r25.uh,{{ *}}#1):sat }
6 v3.w=vdmpy(v3:2.h,r25.uh,#1):sat
11 #CHECK: 1919ccea { v11:10.h = vdmpy(v13:12.ub,{{ *}}r25.b) }
12 v11:10.h=vdmpy(v13:12.ub,r25.b)
Dv60-vmem.s40 #CHECK: 29f9c914 { if (p1) vmem(r25++#1):nt = v20 }
42 if (p1) vmem(r25++#1):nt=v20
95 #CHECK: 2839c316 { vmem(r25+#3) = v22 }
97 vmem(r25+#3)=v22
/external/libunwind/src/ia64/
DGinstall_cursor.S100 ld8 r25 = [r2], 2*LOC_SIZE // r25 = loc[IA64_REG_FR25]
111 and r25 = -4, r25
115 ldf.fill f25 = [r25] // f25 restored (don't touch no more)
193 ld8 r25 = [r3], (FPSR_LOC_OFF - UNAT_LOC_OFF) // r25 = unat_loc
212 and r25 = -4, r25
220 (pRet) ld8 r25 = [r25] // r25 = *unat_loc
292 mov.m ar.unat = r25 // unat restored (don't touch no more)
Ducontext_i.h62 #define rBSP r25
/external/v8/src/regexp/ppc/
Dregexp-macro-assembler-ppc.cc274 __ lbz(r25, MemOperand(r5)); in CheckNotBackReferenceIgnoreCase()
276 __ cmp(r25, r6); in CheckNotBackReferenceIgnoreCase()
281 __ ori(r25, r25, Operand(0x20)); // Also convert input character. in CheckNotBackReferenceIgnoreCase()
282 __ cmp(r25, r6); in CheckNotBackReferenceIgnoreCase()
332 __ mr(r25, r4); in CheckNotBackReferenceIgnoreCase()
336 __ sub(r4, r4, r25); in CheckNotBackReferenceIgnoreCase()
354 __ sub(current_input_offset(), current_input_offset(), r25); in CheckNotBackReferenceIgnoreCase()
356 __ add(current_input_offset(), current_input_offset(), r25); in CheckNotBackReferenceIgnoreCase()
405 __ lbz(r25, MemOperand(r5)); in CheckNotBackReference()
411 __ lhz(r25, MemOperand(r5)); in CheckNotBackReference()
[all …]
/external/libunwind/src/hppa/
DGresume.c39 register unsigned long r25 __asm__ ("r25") = (in_syscall != 0); in my_rt_sigreturn()
46 : "r"(new_sp), "r"(r20), "r"(r25) in my_rt_sigreturn()
/external/llvm/test/Transforms/InstCombine/
Dfold-vector-zero.ll28 %r25 = icmp slt i64 %r23, 0
29 %r26 = zext i1 %r25 to i64
/external/valgrind/coregrind/m_dispatch/
Ddispatch-tilegx-linux.S257 ld r25, r13
264 jr r25
/external/llvm/test/CodeGen/PowerPC/
Dr31.ll6 …4},~{r15},~{r16},~{r17},~{r18},~{r19},~{r20},~{r21},~{r22},~{r23},~{r24},~{r25},~{r26},~{r27},~{r2…
Daantidep-def-ec.mir59 '%r23', '%r24', '%r25', '%r26', '%r27', '%r28',
/external/compiler-rt/lib/tsan/rtl/
Dtsan_ppc_regs.h26 #define r25 25 macro
Dtsan_rtl_ppc64.S87 std r25,112(r3)
232 std r25,112(r3)
/external/valgrind/VEX/auxprogs/
Dgenoffsets.c220 GENOFFSET(MIPS32,mips32,r25); in foo()
257 GENOFFSET(MIPS64,mips64,r25); in foo()
294 GENOFFSET(TILEGX,tilegx,r25); in foo()
/external/llvm/test/MC/PowerPC/
Dppc64-regs.s31 #CHECK: .cfi_offset r25, 208
148 .cfi_offset r25,208
/external/llvm/test/DebugInfo/SystemZ/
Deh_frame.s64 # DW_CFA_offset: r25 at cfa-208
/external/valgrind/VEX/orig_ppc32/
Ddate.orig90 0x25471A88: 93210294 stw r25,660(r1)
360 0x25471B14: 3F206FFF lis r25,28671
395 0x25471B30: 6323FE34 ori r3,r25,0xFE34
552 0x25471E28: 5579083C rlwinm r25,r11,1,0,30
558 0x25471E2C: 7F2C0E70 srawi r12,r25,1
896 0x25471BFC: 83290004 lwz r25,4(r9)
903 0x25471C00: 7D995A14 add r12,r25,r11
1054 0x25480840: 93210014 stw r25,20(r1)
1061 0x25480844: 7C992378 or r25,r4,r4
1280 0x254808C0: 2E190000 cmpi cr4,r25,0
[all …]
Dreturn0.orig90 0x25471A88: 93210294 stw r25,660(r1)
360 0x25471B14: 3F206FFF lis r25,28671
395 0x25471B30: 6323FE34 ori r3,r25,0xFE34
552 0x25471E28: 5579083C rlwinm r25,r11,1,0,30
558 0x25471E2C: 7F2C0E70 srawi r12,r25,1
896 0x25471BFC: 83290004 lwz r25,4(r9)
903 0x25471C00: 7D995A14 add r12,r25,r11
1054 0x25480840: 93210014 stw r25,20(r1)
1061 0x25480844: 7C992378 or r25,r4,r4
1280 0x254808C0: 2E190000 cmpi cr4,r25,0
[all …]
/external/llvm/lib/Target/AVR/
DAVRRegisterInfo.td70 def R25 : AVRReg<25, "r25">, DwarfRegNum<[25]>;
94 def R25R24 : AVRReg<24, "r25:r24", [R24, R25]>, DwarfRegNum<[24]>;
/external/llvm/test/CodeGen/AArch64/
Dghc-cc.ll11 @r4 = external global i64 ; assigned to register: r25
/external/v8/src/compiler/
Dc-linkage.cc118 r20.bit() | r21.bit() | r22.bit() | r23.bit() | r24.bit() | r25.bit() | \
/external/llvm/test/CodeGen/Mips/msa/
Dspill.ll100 %r25 = call <16 x i8> @llvm.mips.addv.b(<16 x i8> %r24, <16 x i8> %25)
101 %r26 = call <16 x i8> @llvm.mips.addv.b(<16 x i8> %r25, <16 x i8> %26)
249 %r25 = call <8 x i16> @llvm.mips.addv.h(<8 x i16> %r24, <8 x i16> %25)
250 %r26 = call <8 x i16> @llvm.mips.addv.h(<8 x i16> %r25, <8 x i16> %26)
398 %r25 = call <4 x i32> @llvm.mips.addv.w(<4 x i32> %r24, <4 x i32> %25)
399 %r26 = call <4 x i32> @llvm.mips.addv.w(<4 x i32> %r25, <4 x i32> %26)
547 %r25 = call <2 x i64> @llvm.mips.addv.d(<2 x i64> %r24, <2 x i64> %25)
548 %r26 = call <2 x i64> @llvm.mips.addv.d(<2 x i64> %r25, <2 x i64> %26)
/external/antlr/antlr-3.4/runtime/Python/tests/
Dt042ast.g122 r25
/external/antlr/antlr-3.4/runtime/JavaScript/tests/functional/
Dt042ast.g128 r25

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