Home
last modified time | relevance | path

Searched refs:reg (Results 1 – 25 of 1230) sorted by relevance

12345678910>>...50

/external/mesa3d/src/gallium/auxiliary/tgsi/
Dtgsi_sanity.c66 scan_register_key(const scan_register *reg) in scan_register_key() argument
68 unsigned key = reg->file; in scan_register_key()
69 key |= (reg->indices[0] << 4); in scan_register_key()
70 key |= (reg->indices[1] << 18); in scan_register_key()
76 fill_scan_register1d(scan_register *reg, in fill_scan_register1d() argument
79 reg->file = file; in fill_scan_register1d()
80 reg->dimensions = 1; in fill_scan_register1d()
81 reg->indices[0] = index; in fill_scan_register1d()
82 reg->indices[1] = 0; in fill_scan_register1d()
86 fill_scan_register2d(scan_register *reg, in fill_scan_register2d() argument
[all …]
Dtgsi_util.c53 const struct tgsi_src_register *reg, in tgsi_util_get_src_register_swizzle() argument
58 return reg->SwizzleX; in tgsi_util_get_src_register_swizzle()
60 return reg->SwizzleY; in tgsi_util_get_src_register_swizzle()
62 return reg->SwizzleZ; in tgsi_util_get_src_register_swizzle()
64 return reg->SwizzleW; in tgsi_util_get_src_register_swizzle()
74 const struct tgsi_full_src_register *reg, in tgsi_util_get_full_src_register_swizzle() argument
78 &reg->Register, in tgsi_util_get_full_src_register_swizzle()
84 struct tgsi_src_register *reg, in tgsi_util_set_src_register_swizzle() argument
90 reg->SwizzleX = swizzle; in tgsi_util_set_src_register_swizzle()
93 reg->SwizzleY = swizzle; in tgsi_util_set_src_register_swizzle()
[all …]
/external/mesa3d/src/mesa/drivers/dri/i965/
Dbrw_clip_line.c53 c->reg.R0 = retype(brw_vec8_grf(i, 0), BRW_REGISTER_TYPE_UD); i++; in brw_clip_line_alloc_regs()
56 c->reg.fixed_planes = brw_vec4_grf(i, 0); in brw_clip_line_alloc_regs()
68 c->reg.vertex[j] = brw_vec4_grf(i, 0); in brw_clip_line_alloc_regs()
72 c->reg.t = brw_vec1_grf(i, 0); in brw_clip_line_alloc_regs()
73 c->reg.t0 = brw_vec1_grf(i, 1); in brw_clip_line_alloc_regs()
74 c->reg.t1 = brw_vec1_grf(i, 2); in brw_clip_line_alloc_regs()
75 c->reg.planemask = retype(brw_vec1_grf(i, 3), BRW_REGISTER_TYPE_UD); in brw_clip_line_alloc_regs()
76 c->reg.plane_equation = brw_vec4_grf(i, 4); in brw_clip_line_alloc_regs()
79 c->reg.dp0 = brw_vec1_grf(i, 0); /* fixme - dp4 will clobber r.1,2,3 */ in brw_clip_line_alloc_regs()
80 c->reg.dp1 = brw_vec1_grf(i, 4); in brw_clip_line_alloc_regs()
[all …]
Dbrw_gs_emit.c63 c->reg.R0 = retype(brw_vec8_grf(i, 0), BRW_REGISTER_TYPE_UD); i++; in brw_gs_alloc_regs()
67 c->reg.SVBI = retype(brw_vec8_grf(i++, 0), BRW_REGISTER_TYPE_UD); in brw_gs_alloc_regs()
72 c->reg.vertex[j] = brw_vec4_grf(i, 0); in brw_gs_alloc_regs()
76 c->reg.header = retype(brw_vec8_grf(i++, 0), BRW_REGISTER_TYPE_UD); in brw_gs_alloc_regs()
77 c->reg.temp = retype(brw_vec8_grf(i++, 0), BRW_REGISTER_TYPE_UD); in brw_gs_alloc_regs()
80 c->reg.destination_indices = in brw_gs_alloc_regs()
106 brw_MOV(p, c->reg.header, c->reg.R0); in brw_gs_initialize_header()
120 brw_MOV(p, get_element_ud(c->reg.header, 2), brw_imm_ud(dw2)); in brw_gs_overwrite_header_dw2()
134 brw_AND(p, get_element_ud(c->reg.header, 2), get_element_ud(c->reg.R0, 2), in brw_gs_overwrite_header_dw2_from_r0()
136 brw_SHL(p, get_element_ud(c->reg.header, 2), in brw_gs_overwrite_header_dw2_from_r0()
[all …]
Dbrw_clip_tri.c58 c->reg.R0 = retype(brw_vec8_grf(i, 0), BRW_REGISTER_TYPE_UD); i++; in brw_clip_tri_alloc_regs()
61 c->reg.fixed_planes = brw_vec4_grf(i, 0); in brw_clip_tri_alloc_regs()
73 c->reg.vertex[j] = brw_vec4_grf(i, 0); in brw_clip_tri_alloc_regs()
84 brw_MOV(&c->func, byte_offset(c->reg.vertex[j], delta), brw_imm_f(0)); in brw_clip_tri_alloc_regs()
88 c->reg.t = brw_vec1_grf(i, 0); in brw_clip_tri_alloc_regs()
89 c->reg.loopcount = retype(brw_vec1_grf(i, 1), BRW_REGISTER_TYPE_D); in brw_clip_tri_alloc_regs()
90 c->reg.nr_verts = retype(brw_vec1_grf(i, 2), BRW_REGISTER_TYPE_UD); in brw_clip_tri_alloc_regs()
91 c->reg.planemask = retype(brw_vec1_grf(i, 3), BRW_REGISTER_TYPE_UD); in brw_clip_tri_alloc_regs()
92 c->reg.plane_equation = brw_vec4_grf(i, 4); in brw_clip_tri_alloc_regs()
95 c->reg.dpPrev = brw_vec1_grf(i, 0); /* fixme - dp4 will clobber r.1,2,3 */ in brw_clip_tri_alloc_regs()
[all …]
Dbrw_eu.h196 struct brw_reg reg; in brw_reg() local
204 reg.type = type; in brw_reg()
205 reg.file = file; in brw_reg()
206 reg.nr = nr; in brw_reg()
207 reg.subnr = subnr * type_sz(type); in brw_reg()
208 reg.negate = 0; in brw_reg()
209 reg.abs = 0; in brw_reg()
210 reg.vstride = vstride; in brw_reg()
211 reg.width = width; in brw_reg()
212 reg.hstride = hstride; in brw_reg()
[all …]
Dbrw_vec4.cpp62 src_reg::src_reg(register_file file, int reg, const glsl_type *type) in src_reg() argument
67 this->reg = reg; in src_reg()
107 src_reg::src_reg(dst_reg reg) in src_reg() argument
111 this->file = reg.file; in src_reg()
112 this->reg = reg.reg; in src_reg()
113 this->reg_offset = reg.reg_offset; in src_reg()
114 this->type = reg.type; in src_reg()
115 this->reladdr = reg.reladdr; in src_reg()
116 this->fixed_hw_reg = reg.fixed_hw_reg; in src_reg()
123 if (!(reg.writemask & (1 << i))) in src_reg()
[all …]
/external/valgrind/VEX/test/
Dmmxtest.c85 #define mmx_m2r(op, mem, reg) \ argument
90 __asm__ __volatile__ ("movq %%" #reg ", %0" \
93 fprintf(stderr, #reg "=0x%016llx) => ", mmx_trace.q); \
94 __asm__ __volatile__ (#op " %0, %%" #reg \
97 __asm__ __volatile__ ("movq %%" #reg ", %0" \
100 fprintf(stderr, #reg "=0x%016llx\n", mmx_trace.q); \
103 #define mmx_r2m(op, reg, mem) \ argument
106 __asm__ __volatile__ ("movq %%" #reg ", %0" \
109 fprintf(stderr, #op "_r2m(" #reg "=0x%016llx, ", mmx_trace.q); \
112 __asm__ __volatile__ (#op " %%" #reg ", %0" \
[all …]
/external/mesa3d/src/mesa/drivers/dri/i915/
Di915_program.c42 #define A0_DEST( reg ) (((reg)&UREG_TYPE_NR_MASK)>>UREG_A0_DEST_SHIFT_LEFT) argument
43 #define D0_DEST( reg ) (((reg)&UREG_TYPE_NR_MASK)>>UREG_A0_DEST_SHIFT_LEFT) argument
44 #define T0_DEST( reg ) (((reg)&UREG_TYPE_NR_MASK)>>UREG_A0_DEST_SHIFT_LEFT) argument
45 #define A0_SRC0( reg ) (((reg)&UREG_MASK)>>UREG_A0_SRC0_SHIFT_LEFT) argument
46 #define A1_SRC0( reg ) (((reg)&UREG_MASK)<<UREG_A1_SRC0_SHIFT_RIGHT) argument
47 #define A1_SRC1( reg ) (((reg)&UREG_MASK)>>UREG_A1_SRC1_SHIFT_LEFT) argument
48 #define A2_SRC1( reg ) (((reg)&UREG_MASK)<<UREG_A2_SRC1_SHIFT_RIGHT) argument
49 #define A2_SRC2( reg ) (((reg)&UREG_MASK)>>UREG_A2_SRC2_SHIFT_LEFT) argument
53 #define T0_SAMPLER( reg ) (GET_UREG_NR(reg)<<T0_SAMPLER_NR_SHIFT) argument
54 #define T1_ADDRESS_REG( reg ) ((GET_UREG_NR(reg)<<T1_ADDRESS_REG_NR_SHIFT) | \ argument
[all …]
/external/mesa3d/src/gallium/drivers/i915/
Di915_fpc_emit.c48 i915_release_temp(struct i915_fp_compile *p, int reg) in i915_release_temp() argument
50 p->temp_flag &= ~(1 << reg); in i915_release_temp()
82 uint reg = UREG(type, nr); in i915_emit_decl() local
86 return reg; in i915_emit_decl()
92 return reg; in i915_emit_decl()
97 return reg; in i915_emit_decl()
100 *(p->decl++) = (D0_DCL | D0_DEST(reg) | d0_flags); in i915_emit_decl()
108 return reg; in i915_emit_decl()
287 unsigned reg, idx; in i915_emit_const1f() local
294 for (reg = 0; reg < I915_MAX_CONSTANT; reg++) { in i915_emit_const1f()
[all …]
Di915_fpc.h127 #define GET_CHANNEL_SRC( reg, channel ) ((reg<<(channel*4)) & (0xf<<20)) argument
130 #define GET_UREG_TYPE(reg) (((reg)>>UREG_TYPE_SHIFT)&REG_TYPE_MASK) argument
131 #define GET_UREG_NR(reg) (((reg)>>UREG_NR_SHIFT)&REG_NR_MASK) argument
140 swizzle(int reg, uint x, uint y, uint z, uint w) in swizzle() argument
146 return ((reg & ~UREG_XYZW_CHANNEL_MASK) | in swizzle()
147 CHANNEL_SRC(GET_CHANNEL_SRC(reg, x), 0) | in swizzle()
148 CHANNEL_SRC(GET_CHANNEL_SRC(reg, y), 1) | in swizzle()
149 CHANNEL_SRC(GET_CHANNEL_SRC(reg, z), 2) | in swizzle()
150 CHANNEL_SRC(GET_CHANNEL_SRC(reg, w), 3)); in swizzle()
154 #define A0_DEST( reg ) (((reg)&UREG_TYPE_NR_MASK)>>UREG_A0_DEST_SHIFT_LEFT) argument
[all …]
/external/libunwind/src/x86_64/
DGstash_frame.c37 rs->reg[DWARF_CFA_REG_COLUMN].where, in tdep_stash_frame()
38 rs->reg[DWARF_CFA_REG_COLUMN].val, in tdep_stash_frame()
39 rs->reg[DWARF_CFA_OFF_COLUMN].val, in tdep_stash_frame()
41 rs->reg[RBP].where, rs->reg[RBP].val, DWARF_GET_LOC(d->loc[RBP]), in tdep_stash_frame()
42 rs->reg[RSP].where, rs->reg[RSP].val, DWARF_GET_LOC(d->loc[RSP])); in tdep_stash_frame()
50 && (rs->reg[DWARF_CFA_REG_COLUMN].where == DWARF_WHERE_REG) in tdep_stash_frame()
51 && (rs->reg[DWARF_CFA_REG_COLUMN].val == RBP in tdep_stash_frame()
52 || rs->reg[DWARF_CFA_REG_COLUMN].val == RSP) in tdep_stash_frame()
53 && labs(rs->reg[DWARF_CFA_OFF_COLUMN].val) < (1 << 29) in tdep_stash_frame()
55 && (rs->reg[RBP].where == DWARF_WHERE_UNDEF in tdep_stash_frame()
[all …]
/external/libunwind/src/ptrace/
D_UPT_access_reg.c41 _UPT_access_reg (unw_addr_space_t as, unw_regnum_t reg, unw_word_t *val, in _UPT_access_reg() argument
48 …Debug(16, "using pokeuser: reg: %s [%u], val: %lx, write: %d\n", unw_regname(reg), (unsigned) reg,… in _UPT_access_reg()
51 Debug (16, "%s <- %lx\n", unw_regname (reg), (long) *val); in _UPT_access_reg()
55 if ((unsigned) reg - UNW_IA64_NAT < 32) in _UPT_access_reg()
60 mask = ((unw_word_t) 1) << (reg - UNW_IA64_NAT); in _UPT_access_reg()
88 switch (reg) in _UPT_access_reg()
139 reg = UNW_IA64_AR_BSP; in _UPT_access_reg()
230 if ((unsigned) reg >= ARRAY_SIZE (_UPT_reg_offset)) in _UPT_access_reg()
245 ptrace (PTRACE_POKEUSER, pid, (void*) (uintptr_t) _UPT_reg_offset[reg], (void*) *val); in _UPT_access_reg()
249 …ug(16, "ptrace PEEKUSER pid: %lu , reg: %lu , offs: %lu\n", (unsigned long)pid, (unsigned long)reg, in _UPT_access_reg()
[all …]
/external/dexmaker/src/dx/java/com/android/dx/rop/code/
DRegisterSpec.java44 private final int reg; field in RegisterSpec
64 private static RegisterSpec intern(int reg, TypeBearer type, in intern() argument
67 theInterningItem.set(reg, type, local); in intern()
90 public static RegisterSpec make(int reg, TypeBearer type) { in make() argument
91 return intern(reg, type, null); in make()
105 public static RegisterSpec make(int reg, TypeBearer type, in make() argument
111 return intern(reg, type, local); in make()
127 int reg, TypeBearer type, LocalItem local) { in makeLocalOptional() argument
129 return intern(reg, type, local); in makeLocalOptional()
138 public static String regString(int reg) { in regString() argument
[all …]
/external/mesa3d/src/gallium/drivers/nv50/codegen/
Dnv50_ir.cpp96 imm.reg.type = type; in getImmediate()
221 memset(&reg, 0, sizeof(reg)); in Value()
222 reg.size = 4; in Value()
227 reg.file = file; in LValue()
228 reg.size = (file != FILE_PREDICATE) ? 4 : 1; in LValue()
229 reg.data.id = -1; in LValue()
244 reg.file = lval->reg.file; in LValue()
245 reg.size = lval->reg.size; in LValue()
246 reg.data.id = -1; in LValue()
260 LValue *that = new_LValue(pol.context(), reg.file); in clone()
[all …]
/external/google-breakpad/src/common/
Ddwarf_cfi_to_module.cc178 unsigned reg = i; in RegisterName() local
179 if (reg == return_address_) in RegisterName()
183 if (reg < register_names_.size() && !register_names_[reg].empty()) in RegisterName()
184 return register_names_[reg]; in RegisterName()
186 reporter_->UnnamedRegister(entry_offset_, reg); in RegisterName()
188 sprintf(buf, "unnamed_register%u", reg); in RegisterName()
192 void DwarfCFIToModule::Record(Module::Address address, int reg, in Record() argument
206 entry_->initial_rules[RegisterName(reg)] = shared_rule; in Record()
209 entry_->rule_changes[address][RegisterName(reg)] = shared_rule; in Record()
212 bool DwarfCFIToModule::UndefinedRule(uint64 address, int reg) { in UndefinedRule() argument
[all …]
/external/libunwind/src/ia64/
DGregs.c31 linux_scratch_loc (struct cursor *c, unw_regnum_t reg, uint8_t *nat_bitnr) in linux_scratch_loc() argument
40 switch (reg) in linux_scratch_loc()
46 *nat_bitnr = (reg - UNW_IA64_NAT); in linux_scratch_loc()
52 addr += LINUX_SC_GR_OFF + 8 * (reg - UNW_IA64_GR); in linux_scratch_loc()
56 addr += LINUX_SC_FR_OFF + 16 * (reg - UNW_IA64_FR); in linux_scratch_loc()
78 addr += LINUX_SC_FR_OFF + 16 * (reg - UNW_IA64_FR); in linux_scratch_loc()
90 if (unw_is_fpreg (reg)) in linux_scratch_loc()
91 return IA64_FPREG_LOC (c, reg); in linux_scratch_loc()
93 return IA64_REG_LOC (c, reg); in linux_scratch_loc()
101 if ((unsigned) (reg - UNW_IA64_NAT) < 128) in linux_scratch_loc()
[all …]
/external/v8/test/unittests/interpreter/
Dbytecode-array-builder-unittest.cc45 Register reg(0); in TEST_F() local
46 builder.LoadAccumulatorWithRegister(reg) in TEST_F()
48 .StoreAccumulatorInRegister(reg); in TEST_F()
52 builder.MoveRegister(reg, other); in TEST_F()
56 builder.ExchangeRegisters(reg, wide); in TEST_F()
57 builder.ExchangeRegisters(wide, reg); in TEST_F()
73 builder.PushContext(reg) in TEST_F()
74 .PopContext(reg) in TEST_F()
75 .LoadContextSlot(reg, 1) in TEST_F()
76 .StoreContextSlot(reg, 1); in TEST_F()
[all …]
/external/mesa3d/src/mesa/drivers/dri/radeon/
Dradeon_sanity.c324 struct reg { struct
336 static struct reg regs[Elements(reg_names)+1]; argument
337 static struct reg scalars[512+1];
338 static struct reg vectors[512*4+1];
372 static int find_or_add_value( struct reg *reg, int val ) in find_or_add_value() argument
376 for ( j = 0 ; j < reg->nvalues ; j++) in find_or_add_value()
377 if ( val == reg->values[j].i ) in find_or_add_value()
380 if (j == reg->nalloc) { in find_or_add_value()
381 reg->nalloc += 5; in find_or_add_value()
382 reg->nalloc *= 2; in find_or_add_value()
[all …]
/external/wpa_supplicant_8/src/wps/
Dwps_registrar.c194 static int wps_set_ie(struct wps_registrar *reg);
198 static void wps_registrar_remove_pin(struct wps_registrar *reg,
202 static void wps_registrar_add_authorized_mac(struct wps_registrar *reg, in wps_registrar_add_authorized_mac() argument
209 if (os_memcmp(reg->authorized_macs[i], addr, ETH_ALEN) == 0) { in wps_registrar_add_authorized_mac()
215 os_memcpy(reg->authorized_macs[i], reg->authorized_macs[i - 1], in wps_registrar_add_authorized_mac()
217 os_memcpy(reg->authorized_macs[0], addr, ETH_ALEN); in wps_registrar_add_authorized_mac()
219 (u8 *) reg->authorized_macs, sizeof(reg->authorized_macs)); in wps_registrar_add_authorized_mac()
223 static void wps_registrar_remove_authorized_mac(struct wps_registrar *reg, in wps_registrar_remove_authorized_mac() argument
230 if (os_memcmp(reg->authorized_macs, addr, ETH_ALEN) == 0) in wps_registrar_remove_authorized_mac()
239 os_memcpy(reg->authorized_macs[i], reg->authorized_macs[i + 1], in wps_registrar_remove_authorized_mac()
[all …]
/external/libunwind/src/ppc64/
DGinit.c46 uc_addr (ucontext_t *uc, int reg) in uc_addr() argument
50 if ((unsigned) (reg - UNW_PPC64_R0) < 32) in uc_addr()
51 addr = &uc->uc_mcontext.gp_regs[reg - UNW_PPC64_R0]; in uc_addr()
53 else if ((unsigned) (reg - UNW_PPC64_F0) < 32) in uc_addr()
54 addr = &uc->uc_mcontext.fp_regs[reg - UNW_PPC64_F0]; in uc_addr()
56 else if ((unsigned) (reg - UNW_PPC64_V0) < 32) in uc_addr()
57 …addr = (uc->uc_mcontext.v_regs == 0) ? NULL : &uc->uc_mcontext.v_regs->vrregs[reg - UNW_PPC64_V0][… in uc_addr()
63 switch (reg) in uc_addr()
91 tdep_uc_addr (ucontext_t *uc, int reg) in tdep_uc_addr() argument
93 return uc_addr (uc, reg); in tdep_uc_addr()
[all …]
/external/libpcap/msdos/
Dpktdrvr.c150 LOCAL SWI_REGS reg; variable
156 static __dpmi_regs reg; variable
171 LOCAL struct DPMI_regs reg; variable
185 } reg; variable
312 _dx_real_int ((UINT)pktInfo.intr, &reg); in PktInterrupt()
313 okay = ((reg.flags & 1) == 0); /* OK if carry clear */ in PktInterrupt()
316 __dpmi_int ((int)pktInfo.intr, &reg); in PktInterrupt()
317 okay = ((reg.x.flags & 1) == 0); in PktInterrupt()
328 s.es = FP_SEG (&reg); in PktInterrupt()
329 r.x.edi = FP_OFF (&reg); in PktInterrupt()
[all …]
/external/mesa3d/src/mesa/drivers/dri/r200/
Dr200_fragshader.c328 GLuint reg; in r200UpdateFSRouting() local
333 for (reg = 0; reg < R200_MAX_TEXTURE_UNITS; reg++) { in r200UpdateFSRouting()
334 if (shader->swizzlerq & (1 << (2 * reg))) in r200UpdateFSRouting()
336 set_re_cntl_d3d( ctx, reg, 1); in r200UpdateFSRouting()
338 else set_re_cntl_d3d( ctx, reg, 0); in r200UpdateFSRouting()
364 for (reg = 0; reg < R200_MAX_TEXTURE_UNITS; reg++) { in r200UpdateFSRouting()
365 GLbitfield targetbit = ctx->Texture.Unit[reg]._ReallyEnabled; in r200UpdateFSRouting()
366 R200_STATECHANGE( rmesa, tex[reg] ); in r200UpdateFSRouting()
367 rmesa->hw.tex[reg].cmd[TEX_PP_TXMULTI_CTL] = 0; in r200UpdateFSRouting()
368 if (shader->SetupInst[0][reg].Opcode) { in r200UpdateFSRouting()
[all …]
/external/libunwind_llvm/src/
DDwarfParser.hpp379 uint64_t reg; in parseInstructions() local
420 reg = addressSpace.getULEB128(p, instructionsEnd); in parseInstructions()
423 if (reg > kMaxRegisterNumber) { in parseInstructions()
428 results->savedRegisters[reg].location = kRegisterInCFA; in parseInstructions()
429 results->savedRegisters[reg].value = offset; in parseInstructions()
433 reg, offset); in parseInstructions()
436 reg = addressSpace.getULEB128(p, instructionsEnd); in parseInstructions()
438 if (reg > kMaxRegisterNumber) { in parseInstructions()
444 results->savedRegisters[reg] = initialState.savedRegisters[reg]; in parseInstructions()
446 fprintf(stderr, "DW_CFA_restore_extended(reg=%" PRIu64 ")\n", reg); in parseInstructions()
[all …]
/external/autotest/client/common_lib/
Di2c_slave.py125 def writeByte(self, reg, byte): argument
137 logging.info('Attempt to write byte %r to reg %r', byte, reg)
138 if self.lib_obj.WriteByte(self.fd, reg, byte) < 0:
139 raise I2cError('Error writing byte 0x%x to reg %r' % (byte, reg))
141 logging.info('Successfully wrote byte 0x%x to reg %r', byte, reg)
143 def readByte(self, reg): argument
157 logging.info('Attempt to read byte from register %r', reg)
158 byte_read = self.lib_obj.ReadByte(self.fd, reg)
160 raise I2cError('Error reading byte from reg %r' % reg)
163 byte_read, reg)
[all …]

12345678910>>...50