Home
last modified time | relevance | path

Searched refs:reg1 (Results 1 – 25 of 86) sorted by relevance

1234

/external/libvpx/libvpx/vpx_dsp/mips/
Didct32x32_msa.c44 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in idct32x8_row_even_process_store() local
48 LD_SH8(tmp_buf, 32, reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7); in idct32x8_row_even_process_store()
50 DOTP_CONST_PAIR(reg1, reg7, cospi_28_64, cospi_4_64, reg1, reg7); in idct32x8_row_even_process_store()
52 BUTTERFLY_4(reg1, reg7, reg3, reg5, vec1, vec3, vec2, vec0); in idct32x8_row_even_process_store()
65 LD_SH8((tmp_buf + 16), 32, reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7); in idct32x8_row_even_process_store()
69 DOTP_CONST_PAIR(reg6, reg1, cospi_6_64, cospi_26_64, reg6, reg1); in idct32x8_row_even_process_store()
75 reg2 = reg1 + reg5; in idct32x8_row_even_process_store()
76 reg1 = reg1 - reg5; in idct32x8_row_even_process_store()
88 DOTP_CONST_PAIR((-reg6), reg1, cospi_24_64, cospi_8_64, reg6, reg1); in idct32x8_row_even_process_store()
92 vec1 = reg7 - reg1; in idct32x8_row_even_process_store()
[all …]
Didct16x16_msa.c16 v8i16 reg3, reg13, reg11, reg5, reg7, reg9, reg1, reg15; in vpx_idct16_1d_rows_msa() local
19 LD_SH8(input, 16, reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7); in vpx_idct16_1d_rows_msa()
23 TRANSPOSE8x8_SH_SH(reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, in vpx_idct16_1d_rows_msa()
24 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7); in vpx_idct16_1d_rows_msa()
40 DOTP_CONST_PAIR(reg1, reg15, cospi_30_64, cospi_2_64, reg1, reg15); in vpx_idct16_1d_rows_msa()
43 reg9 = reg1 - loc2; in vpx_idct16_1d_rows_msa()
44 reg1 = reg1 + loc2; in vpx_idct16_1d_rows_msa()
57 loc1 = reg1 + reg13; in vpx_idct16_1d_rows_msa()
58 reg13 = reg1 - reg13; in vpx_idct16_1d_rows_msa()
71 reg1 = reg6 - loc0; in vpx_idct16_1d_rows_msa()
[all …]
Dtxfm_macros_msa.h16 #define DOTP_CONST_PAIR(reg0, reg1, cnst0, cnst1, out0, out1) { \ argument
23 ILVRL_H2_SW((-reg1), reg0, s1_m, s0_m); \
24 ILVRL_H2_SW(reg0, reg1, s3_m, s2_m); \
/external/libavc/common/armv8/
Dih264_neon_macros.s36 .macro swp reg1, reg2
37 eor \reg1, \reg1, \reg2
38 eor \reg2, \reg1, \reg2
39 eor \reg1, \reg1, \reg2
/external/libmpeg2/common/armv8/
Dimpeg2_neon_macros.s53 .macro swp reg1, reg2
54 eor \reg1, \reg1, \reg2
55 eor \reg2, \reg1, \reg2
56 eor \reg1, \reg1, \reg2
/external/llvm/test/CodeGen/AMDGPU/
Dmax-literals.ll6 define void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2) #0 {
8 %0 = extractelement <4 x float> %reg1, i32 0
9 %1 = extractelement <4 x float> %reg1, i32 1
10 %2 = extractelement <4 x float> %reg1, i32 2
11 %3 = extractelement <4 x float> %reg1, i32 3
35 define void @main2(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2) #0 {
37 %0 = extractelement <4 x float> %reg1, i32 0
38 %1 = extractelement <4 x float> %reg1, i32 1
39 %2 = extractelement <4 x float> %reg1, i32 2
40 %3 = extractelement <4 x float> %reg1, i32 3
Drv7x0_count3.ll5 define void @test(<4 x float> inreg %reg0, <4 x float> inreg %reg1) #0 {
6 %1 = extractelement <4 x float> %reg1, i32 0
7 %2 = extractelement <4 x float> %reg1, i32 1
8 %3 = extractelement <4 x float> %reg1, i32 2
9 %4 = extractelement <4 x float> %reg1, i32 3
Dswizzle-export.ll9 define void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1) #0 {
11 %0 = extractelement <4 x float> %reg1, i32 0
12 %1 = extractelement <4 x float> %reg1, i32 1
13 %2 = extractelement <4 x float> %reg1, i32 2
14 %3 = extractelement <4 x float> %reg1, i32 3
99 define void @main2(<4 x float> inreg %reg0, <4 x float> inreg %reg1) #0 {
101 %0 = extractelement <4 x float> %reg1, i32 0
102 %1 = extractelement <4 x float> %reg1, i32 1
Dpv-packing.ll6 define void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2, <4 x f…
8 %0 = extractelement <4 x float> %reg1, i32 0
9 %1 = extractelement <4 x float> %reg1, i32 1
10 %2 = extractelement <4 x float> %reg1, i32 2
Dschedule-fs-loop-nested-if.ll4 define void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1) #1 {
6 %0 = extractelement <4 x float> %reg1, i32 0
7 %1 = extractelement <4 x float> %reg1, i32 1
8 %2 = extractelement <4 x float> %reg1, i32 2
9 %3 = extractelement <4 x float> %reg1, i32 3
Dr600cfg.ll3 define void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1) #0 {
5 %0 = extractelement <4 x float> %reg1, i32 0
6 %1 = extractelement <4 x float> %reg1, i32 1
7 %2 = extractelement <4 x float> %reg1, i32 2
8 %3 = extractelement <4 x float> %reg1, i32 3
Dload-input-fold.ll3 define void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2, <4 x f…
5 %0 = extractelement <4 x float> %reg1, i32 0
6 %1 = extractelement <4 x float> %reg1, i32 1
7 %2 = extractelement <4 x float> %reg1, i32 2
8 %3 = extractelement <4 x float> %reg1, i32 3
Dschedule-vs-if-nested-loop.ll4 define void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1) #0 {
6 %0 = extractelement <4 x float> %reg1, i32 0
7 %1 = extractelement <4 x float> %reg1, i32 1
8 %2 = extractelement <4 x float> %reg1, i32 2
9 %3 = extractelement <4 x float> %reg1, i32 3
Dshared-op-cycle.ll7 define void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2) #0 {
9 %w1 = extractelement <4 x float> %reg1, i32 3
Dschedule-vs-if-nested-loop-failure.ll10 define void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1) #0 {
12 %0 = extractelement <4 x float> %reg1, i32 0
13 %1 = extractelement <4 x float> %reg1, i32 2
40 %15 = extractelement <4 x float> %reg1, i32 1
41 %16 = extractelement <4 x float> %reg1, i32 3
/external/boringssl/src/crypto/perlasm/
Dx86gas.pl70 { my($addr,$reg1,$reg2,$idx)=@_;
73 if (!defined($idx) && 1*$reg2) { $idx=$reg2; $reg2=$reg1; undef $reg1; }
79 $reg1 = "%$reg1" if ($reg1);
86 $ret .= "($reg1,$reg2,$idx)";
88 elsif ($reg1)
89 { $ret .= "($reg1)"; }
Dx86nasm.pl36 { my($size,$addr,$reg1,$reg2,$idx)=@_;
39 if (!defined($idx) && 1*$reg2) { $idx=$reg2; $reg2=$reg1; undef $reg1; }
62 $ret .= "+$reg1" if ($reg1 ne "");
65 { $ret .= "$reg1"; }
Dx86masm.pl39 { my($size,$addr,$reg1,$reg2,$idx)=@_;
42 if (!defined($idx) && 1*$reg2) { $idx=$reg2; $reg2=$reg1; undef $reg1; }
61 $ret .= "+$reg1" if ($reg1 ne "");
64 { $ret .= "$reg1"; }
/external/mesa3d/src/mesa/program/
Dregister_allocate.c189 struct ra_reg *reg1 = &regs->regs[r1]; in ra_add_conflict_list() local
191 if (reg1->conflict_list_size == reg1->num_conflicts) { in ra_add_conflict_list()
192 reg1->conflict_list_size *= 2; in ra_add_conflict_list()
193 reg1->conflict_list = reralloc(regs->regs, reg1->conflict_list, in ra_add_conflict_list()
194 unsigned int, reg1->conflict_list_size); in ra_add_conflict_list()
196 reg1->conflict_list[reg1->num_conflicts++] = r2; in ra_add_conflict_list()
197 reg1->conflicts[r2] = GL_TRUE; in ra_add_conflict_list()
/external/llvm/test/CodeGen/X86/
Dcopy-propagation.ll10 ; reg1 = copy reg2
12 ; reg2 = copy reg1
17 ; reg1 = copy reg2
20 ; reg2 = copy reg1
/external/libunwind/src/ptrace/
D_UPT_access_mem.c63 long reg1, reg2; in _UPT_access_mem()
64 reg1 = ptrace (PTRACE_PEEKDATA, pid, (void*) (uintptr_t) addr, 0); in _UPT_access_mem()
70 *val = ((unw_word_t)(reg2) << 32) | (uint32_t) reg1; in _UPT_access_mem()
/external/aac/libFDK/src/
Dfixpoint_math.cpp430 FIXP_DBL reg1, reg2, regtmp ; in invSqrtNorm2() local
445 reg1 = invSqrtTab[ (INT)(val>>(DFRACT_BITS-1-(SQRT_BITS+1))) & SQRT_BITS_MASK ]; in invSqrtNorm2()
448 regtmp= fPow2Div2(reg1); /* a = Q^2 */ in invSqrtNorm2()
450 reg1 += (fMultDiv2(regtmp, reg1)<<4); /* Q = Q + Q*b */ in invSqrtNorm2()
455 reg1 = fMultDiv2(reg1, reg2) << 2; in invSqrtNorm2()
460 return(reg1); in invSqrtNorm2()
/external/webrtc/webrtc/system_wrappers/include/
Dasm_defines.h59 .macro streqh reg1, reg2, num
60 strheq \reg1, \reg2, \num
/external/v8/test/unittests/interpreter/
Dbytecode-register-allocator-unittest.cc57 Register reg1 = temporaries.NextConsecutiveRegister(); in TEST_F() local
62 CHECK(Register::AreContiguous(reg0, reg1, reg2, reg3)); in TEST_F()
/external/llvm/test/CodeGen/ARM/
Dfast-isel-pic.ll19 ; ARM: ldr [[reg1:r[0-9]+]],
20 ; ARM: add [[reg1]], pc, [[reg1]]

1234