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Searched refs:reg2 (Results 1 – 25 of 68) sorted by relevance

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/external/libvpx/libvpx/vpx_dsp/mips/
Didct32x32_msa.c44 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in idct32x8_row_even_process_store() local
48 LD_SH8(tmp_buf, 32, reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7); in idct32x8_row_even_process_store()
59 DOTP_CONST_PAIR(reg2, reg6, cospi_24_64, cospi_8_64, reg2, reg6); in idct32x8_row_even_process_store()
60 BUTTERFLY_4(reg4, reg0, reg2, reg6, vec1, vec3, vec2, vec0); in idct32x8_row_even_process_store()
65 LD_SH8((tmp_buf + 16), 32, reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7); in idct32x8_row_even_process_store()
68 DOTP_CONST_PAIR(reg2, reg5, cospi_22_64, cospi_10_64, reg2, reg5); in idct32x8_row_even_process_store()
73 reg4 = reg6 + reg2; in idct32x8_row_even_process_store()
74 reg6 = reg6 - reg2; in idct32x8_row_even_process_store()
75 reg2 = reg1 + reg5; in idct32x8_row_even_process_store()
81 vec1 = reg2; in idct32x8_row_even_process_store()
[all …]
Didct16x16_msa.c15 v8i16 reg0, reg2, reg4, reg6, reg8, reg10, reg12, reg14; in vpx_idct16_1d_rows_msa() local
19 LD_SH8(input, 16, reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7); in vpx_idct16_1d_rows_msa()
23 TRANSPOSE8x8_SH_SH(reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, in vpx_idct16_1d_rows_msa()
24 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7); in vpx_idct16_1d_rows_msa()
27 DOTP_CONST_PAIR(reg2, reg14, cospi_28_64, cospi_4_64, reg2, reg14); in vpx_idct16_1d_rows_msa()
29 BUTTERFLY_4(reg2, reg14, reg6, reg10, loc0, loc1, reg14, reg2); in vpx_idct16_1d_rows_msa()
30 DOTP_CONST_PAIR(reg14, reg2, cospi_16_64, cospi_16_64, loc2, loc3); in vpx_idct16_1d_rows_msa()
33 BUTTERFLY_4(reg8, reg0, reg4, reg12, reg2, reg6, reg10, reg14); in vpx_idct16_1d_rows_msa()
34 SUB4(reg2, loc1, reg14, loc0, reg6, loc3, reg10, loc2, reg0, reg12, reg4, in vpx_idct16_1d_rows_msa()
36 ADD4(reg2, loc1, reg14, loc0, reg6, loc3, reg10, loc2, reg2, reg14, reg6, in vpx_idct16_1d_rows_msa()
[all …]
/external/llvm/test/CodeGen/X86/
Dcopy-propagation.ll10 ; reg1 = copy reg2
11 ; = inst reg2<undef>
12 ; reg2 = copy reg1
14 ; This is incorrect because the undef flag on reg2 in inst, allows next
15 ; passes to put whatever trashed value in reg2 that may help.
17 ; reg1 = copy reg2
18 ; reg2 = 0
19 ; = inst reg2<undef>
20 ; reg2 = copy reg1
Davoid_complex_am.ll4 ; On X86, reg1 + 1*reg2 has the same cost as reg1 + 8*reg2.
/external/libavc/common/armv8/
Dih264_neon_macros.s36 .macro swp reg1, reg2 argument
37 eor \reg1, \reg1, \reg2
38 eor \reg2, \reg1, \reg2
39 eor \reg1, \reg1, \reg2
/external/libmpeg2/common/armv8/
Dimpeg2_neon_macros.s53 .macro swp reg1, reg2 argument
54 eor \reg1, \reg1, \reg2
55 eor \reg2, \reg1, \reg2
56 eor \reg1, \reg1, \reg2
/external/llvm/test/CodeGen/ARM/
Dfast-isel-pic.ll22 ; ARMv7: movw [[reg2:r[0-9]+]],
23 ; ARMv7: movt [[reg2]],
24 ; ARMv7: add [[reg2]], pc, [[reg2]]
26 ; ARMv7-ELF: ldr r[[reg2:[0-9]+]],
28 ; ARMv7-ELF-NEXT: ldr r[[reg2]], [pc, r[[reg2]]]
29 ; ARMv7-ELF: ldr r[[reg2]], [r[[reg2]]]
/external/boringssl/src/crypto/perlasm/
Dx86gas.pl70 { my($addr,$reg1,$reg2,$idx)=@_;
73 if (!defined($idx) && 1*$reg2) { $idx=$reg2; $reg2=$reg1; undef $reg1; }
80 $reg2 = "%$reg2" if ($reg2);
84 if ($reg2)
86 $ret .= "($reg1,$reg2,$idx)";
Dx86nasm.pl36 { my($size,$addr,$reg1,$reg2,$idx)=@_;
39 if (!defined($idx) && 1*$reg2) { $idx=$reg2; $reg2=$reg1; undef $reg1; }
59 if ($reg2 ne "")
61 $ret .= "$reg2*$idx";
Dx86masm.pl39 { my($size,$addr,$reg1,$reg2,$idx)=@_;
42 if (!defined($idx) && 1*$reg2) { $idx=$reg2; $reg2=$reg1; undef $reg1; }
58 if ($reg2 ne "")
60 $ret .= "$reg2*$idx";
/external/llvm/test/CodeGen/AMDGPU/
Dpv-packing.ll6 define void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2, <4 x f…
11 %3 = extractelement <4 x float> %reg2, i32 0
12 %4 = extractelement <4 x float> %reg2, i32 1
13 %5 = extractelement <4 x float> %reg2, i32 2
Dmax-literals.ll6 define void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2) #0 {
12 %4 = extractelement <4 x float> %reg2, i32 0
35 define void @main2(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2) #0 {
41 %4 = extractelement <4 x float> %reg2, i32 0
Dload-input-fold.ll3 define void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2, <4 x f…
9 %4 = extractelement <4 x float> %reg2, i32 0
10 %5 = extractelement <4 x float> %reg2, i32 1
11 %6 = extractelement <4 x float> %reg2, i32 2
12 %7 = extractelement <4 x float> %reg2, i32 3
Dshared-op-cycle.ll7 define void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2) #0 {
10 %w2 = extractelement <4 x float> %reg2, i32 3
Dpv.ll6 define void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2, <4 x f…
12 %4 = extractelement <4 x float> %reg2, i32 0
13 %5 = extractelement <4 x float> %reg2, i32 1
14 %6 = extractelement <4 x float> %reg2, i32 2
15 %7 = extractelement <4 x float> %reg2, i32 3
/external/libunwind/src/ptrace/
D_UPT_access_mem.c63 long reg1, reg2; in _UPT_access_mem()
67 reg2 = ptrace (PTRACE_PEEKDATA, pid, (void*) (uintptr_t) (addr + sizeof(long)), 0); in _UPT_access_mem()
70 *val = ((unw_word_t)(reg2) << 32) | (uint32_t) reg1; in _UPT_access_mem()
/external/webrtc/webrtc/system_wrappers/include/
Dasm_defines.h59 .macro streqh reg1, reg2, num
60 strheq \reg1, \reg2, \num
/external/v8/test/unittests/interpreter/
Dbytecode-register-allocator-unittest.cc58 Register reg2 = temporaries.NextConsecutiveRegister(); in TEST_F() local
62 CHECK(Register::AreContiguous(reg0, reg1, reg2, reg3)); in TEST_F()
/external/mesa3d/src/mesa/drivers/dri/r200/
Dr200_fragshader.c49 GLuint reg2 = 0; in r200SetFragShaderArg() local
54 reg2 |= R200_TXC_REPL_RED << (R200_TXC_REPL_ARG_A_SHIFT + (2*argPos)); in r200SetFragShaderArg()
59 reg2 |= R200_TXC_REPL_GREEN << (R200_TXC_REPL_ARG_A_SHIFT + (2*argPos)); in r200SetFragShaderArg()
65 reg2 |= R200_TXC_REPL_BLUE << (R200_TXC_REPL_ARG_A_SHIFT + (2*argPos)); in r200SetFragShaderArg()
80 reg2 |= (index - GL_CON_0_ATI) << R200_TXC_TFACTOR_SEL_SHIFT; in r200SetFragShaderArg()
85 reg2 |= (index - GL_CON_0_ATI) << R200_TXC_TFACTOR1_SEL_SHIFT; in r200SetFragShaderArg()
109 SET_INST_2(opnum, optype) |= reg2; in r200SetFragShaderArg()
/external/valgrind/none/tests/s390x/
Dcksm.c26 register uint64_t reg2 asm("2") = (uint64_t) buff; in cksm_by_insn()
33 : "+d" (sum), "+d" (reg2), "+d" (reg3) : : "cc", "memory"); in cksm_by_insn()
37 addr = reg2; in cksm_by_insn()
/external/aac/libFDK/src/
Dfixpoint_math.cpp430 FIXP_DBL reg1, reg2, regtmp ; in invSqrtNorm2() local
446 reg2 = FL2FXCONST_DBL(0.0625f); /* 0.5 >> 3 */ in invSqrtNorm2()
449 regtmp= reg2 - fMultDiv2(regtmp, val); /* b = 0.5 - 2 * V * Q^2 */ in invSqrtNorm2()
454 reg2 = FL2FXCONST_DBL(0.707106781186547524400844362104849f); /* 1/sqrt(2); */ in invSqrtNorm2()
455 reg1 = fMultDiv2(reg1, reg2) << 2; in invSqrtNorm2()
/external/llvm/test/MC/MachO/
Dbad-macro.s5 .macro test_macro reg1, reg2 argument
/external/v8/src/interpreter/
Dbytecodes.cc434 bool Register::AreContiguous(Register reg1, Register reg2, Register reg3, in AreContiguous() argument
436 if (reg1.index() + 1 != reg2.index()) { in AreContiguous()
439 if (reg3.is_valid() && reg2.index() + 1 != reg3.index()) { in AreContiguous()
/external/libunwind_llvm/src/
DDwarfParser.hpp380 uint64_t reg2; in parseInstructions() local
478 reg2 = addressSpace.getULEB128(p, instructionsEnd); in parseInstructions()
484 if (reg2 > kMaxRegisterNumber) { in parseInstructions()
490 results->savedRegisters[reg].value = (int64_t)reg2; in parseInstructions()
495 reg, reg2); in parseInstructions()
/external/llvm/lib/Target/AArch64/
DAArch64PBQPRegAlloc.cpp150 bool haveSameParity(unsigned reg1, unsigned reg2) { in haveSameParity() argument
152 assert(isFPReg(reg2) && "Expecting an FP register for reg2"); in haveSameParity()
154 return isOdd(reg1) == isOdd(reg2); in haveSameParity()

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