| /external/libvpx/libvpx/vpx_dsp/mips/ |
| D | idct16x16_msa.c | 333 v8i16 res8, res9, res10, res11, res12, res13, res14, res15; in vpx_iadst16_1d_columns_addblk_msa() local
457 ILVR_B2_SH(zero, dst10, zero, dst11, res10, res11); in vpx_iadst16_1d_columns_addblk_msa()
458 ADD2(res10, out10, res11, out11, res10, res11); in vpx_iadst16_1d_columns_addblk_msa()
459 CLIP_SH2_0_255(res10, res11); in vpx_iadst16_1d_columns_addblk_msa()
460 PCKEV_B2_SH(res10, res10, res11, res11, res10, res11); in vpx_iadst16_1d_columns_addblk_msa()
462 ST8x1_UB(res11, dst + 9 * dst_stride); in vpx_iadst16_1d_columns_addblk_msa()
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| /external/llvm/test/CodeGen/AMDGPU/ |
| D | llvm.SI.resinfo.ll | 33 %res11 = call <4 x i32> @llvm.SI.resinfo(i32 %a11, <32 x i8> undef, i32 11)
61 %t12 = extractelement <4 x i32> %res11, i32 0
62 %t13 = extractelement <4 x i32> %res11, i32 1
63 %t14 = extractelement <4 x i32> %res11, i32 2
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| D | llvm.SI.imageload.ll | 40 %res11 = call <4 x i32> @llvm.SI.imageload.(<4 x i32> %v11,
59 %t12 = extractelement <4 x i32> %res11, i32 0
60 %t13 = extractelement <4 x i32> %res11, i32 1
61 %t14 = extractelement <4 x i32> %res11, i32 2
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| D | llvm.SI.sampled.ll | 58 %res11 = call <4 x float> @llvm.SI.sampled.(<4 x i32> %v11,
92 %t12 = extractelement <4 x float> %res11, i32 0
93 %t13 = extractelement <4 x float> %res11, i32 1
94 %t14 = extractelement <4 x float> %res11, i32 2
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| D | llvm.SI.sample.ll | 58 %res11 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v11,
92 %t12 = extractelement <4 x float> %res11, i32 0
93 %t13 = extractelement <4 x float> %res11, i32 1
94 %t14 = extractelement <4 x float> %res11, i32 2
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| D | llvm.AMDGPU.tex.ll | 32 %res11 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %res10, i32 0, i32 0, i32 11)
33 %res12 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %res11, i32 0, i32 0, i32 12)
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| D | fetch-limits.r700+.ll | 49 %res11 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %11, i32 0, i32 0, i32 1)
60 %f = fadd <4 x float> %res10, %res11
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| /external/llvm/test/Bitcode/ |
| D | miscInstructions.3.2.ll | 105 ; CHECK-NEXT: %res11 = icmp eq i32* %ptr1, %ptr2
106 %res11 = icmp eq i32* %ptr1, %ptr2
147 ; CHECK-NEXT: %res11 = fcmp ord float %x1, %x2
148 %res11 = fcmp ord float %x1, %x2
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| D | memInstructions.3.2.ll | 60 ; CHECK-NEXT: %res11 = load i8, i8* %ptr1, align 1, !invariant.load !1
61 %res11 = load i8, i8* %ptr1, align 1, !invariant.load !1
116 ; CHECK-NEXT: %res11 = load atomic i8, i8* %ptr1 singlethread acquire, align 1
117 %res11 = load atomic i8, i8* %ptr1 singlethread acquire, align 1
270 ; CHECK-NEXT: %res11 = extractvalue { i32, i1 } [[TMP]], 0
271 %res11 = cmpxchg i32* %ptr, i32 %cmp, i32 %new singlethread release monotonic
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| /external/clang/test/SemaCXX/ |
| D | altivec.cpp | 30 int res11[vec_step(vui) == 4 ? 1 : -1]; in test_vec_step() local
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| /external/clang/test/SemaOpenCL/ |
| D | vec_step.cl | 26 int res11[vec_step(int16) == 16 ? 1 : -1];
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| /external/libvpx/libvpx/vpx_dsp/x86/ |
| D | fwd_txfm_impl_sse2.h | 630 __m128i res08, res09, res10, res11, res12, res13, res14, res15; in FDCT16x16_2D() local
995 res11 = mult_round_shift(&t0, &t1, &k__cospi_m10_p22, in FDCT16x16_2D()
1000 overflow = check_epi16_overflow_x4(&res05, &res13, &res11, &res03); in FDCT16x16_2D()
1012 transpose_and_output8x8(&res08, &res09, &res10, &res11, in FDCT16x16_2D()
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| /external/llvm/test/CodeGen/X86/ |
| D | avx512-intrinsics.ll | 5590 %res11 = or i8 %res1, %res2
5592 %res13 = or i8 %res11, %res12
5634 %res11 = and i8 %res1, %res2
5636 %res13 = and i8 %res11, %res12
5764 %res11 = fadd <2 x double> %res, %res1
5766 %res13 = fadd <2 x double> %res11, %res12
5789 %res11 = fadd <4 x float> %res, %res1
5791 %res13 = fadd <4 x float> %res11, %res12
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