Home
last modified time | relevance | path

Searched refs:res15 (Results 1 – 11 of 11) sorted by relevance

/external/llvm/test/CodeGen/AMDGPU/
Dllvm.SI.resinfo.ll37 %res15 = call <4 x i32> @llvm.SI.resinfo(i32 %a15, <32 x i8> undef, i32 15)
81 %t28 = extractelement <4 x i32> %res15, i32 0
82 %t29 = extractelement <4 x i32> %res15, i32 1
83 %t30 = extractelement <4 x i32> %res15, i32 2
84 %t31 = extractelement <4 x i32> %res15, i32 3
Dllvm.SI.imageload.ll42 %res15 = call <4 x i32> @llvm.SI.imageload.(<4 x i32> %v15,
64 %t28 = extractelement <4 x i32> %res15, i32 0
65 %t29 = extractelement <4 x i32> %res15, i32 1
66 %t30 = extractelement <4 x i32> %res15, i32 2
67 %t31 = extractelement <4 x i32> %res15, i32 3
Dllvm.SI.sampled.ll66 %res15 = call <4 x float> @llvm.SI.sampled.(<4 x i32> %v15,
112 %t28 = extractelement <4 x float> %res15, i32 0
113 %t29 = extractelement <4 x float> %res15, i32 1
114 %t30 = extractelement <4 x float> %res15, i32 2
115 %t31 = extractelement <4 x float> %res15, i32 3
Dllvm.SI.sample.ll66 %res15 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v15,
112 %t28 = extractelement <4 x float> %res15, i32 0
113 %t29 = extractelement <4 x float> %res15, i32 1
114 %t30 = extractelement <4 x float> %res15, i32 2
115 %t31 = extractelement <4 x float> %res15, i32 3
Dllvm.AMDGPU.tex.ll36 %res15 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %res14, i32 0, i32 0, i32 15)
37 %res16 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %res15, i32 0, i32 0, i32 16)
Dfetch-limits.r700+.ll53 %res15 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %15, i32 0, i32 0, i32 1)
62 %h = fadd <4 x float> %res14, %res15
/external/libvpx/libvpx/vpx_dsp/mips/
Didct16x16_msa.c333 v8i16 res8, res9, res10, res11, res12, res13, res14, res15; in vpx_iadst16_1d_columns_addblk_msa() local
481 ILVR_B2_SH(zero, dst14, zero, dst15, res14, res15); in vpx_iadst16_1d_columns_addblk_msa()
482 ADD2(res14, out14, res15, out15, res14, res15); in vpx_iadst16_1d_columns_addblk_msa()
483 CLIP_SH2_0_255(res14, res15); in vpx_iadst16_1d_columns_addblk_msa()
484 PCKEV_B2_SH(res14, res14, res15, res15, res14, res15); in vpx_iadst16_1d_columns_addblk_msa()
486 ST8x1_UB(res15, dst + 10 * dst_stride); in vpx_iadst16_1d_columns_addblk_msa()
/external/llvm/test/Bitcode/
DmemInstructions.3.2.ll72 ; CHECK-NEXT: %res15 = load i8, i8* %ptr1, align 1, {{[(!nontemporal !0, !invariant.load !1) | (!in…
73 %res15 = load i8, i8* %ptr1, align 1, !nontemporal !0, !invariant.load !1
128 ; CHECK-NEXT: %res15 = load atomic volatile i8, i8* %ptr1 singlethread acquire, align 1
129 %res15 = load atomic volatile i8, i8* %ptr1 singlethread acquire, align 1
287 ; CHECK-NEXT: %res15 = extractvalue { i32, i1 } [[TMP]], 0
288 %res15 = cmpxchg i32* %ptr, i32 %cmp, i32 %new singlethread acq_rel acquire
DmiscInstructions.3.2.ll159 ; CHECK-NEXT: %res15 = fcmp true float %x1, %x2
160 %res15 = fcmp true float %x1, %x2
/external/clang/test/SemaOpenCL/
Dvec_step.cl31 …int res15 = vec_step(void(void)); // expected-error {{'vec_step' requires built-in scalar or vecto…
/external/libvpx/libvpx/vpx_dsp/x86/
Dfwd_txfm_impl_sse2.h630 __m128i res08, res09, res10, res11, res12, res13, res14, res15; in FDCT16x16_2D() local
974 res15 = mult_round_shift(&t0, &t1, &k__cospi_m02_p30, in FDCT16x16_2D()
979 overflow = check_epi16_overflow_x4(&res01, &res09, &res15, &res07); in FDCT16x16_2D()
1013 &res12, &res13, &res14, &res15, in FDCT16x16_2D()