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Searched refs:res9 (Results 1 – 11 of 11) sorted by relevance

/external/libvpx/libvpx/vpx_dsp/mips/
Didct16x16_msa.c333 v8i16 res8, res9, res10, res11, res12, res13, res14, res15; in vpx_iadst16_1d_columns_addblk_msa() local
406 ILVR_B2_SH(zero, dst8, zero, dst9, res8, res9); in vpx_iadst16_1d_columns_addblk_msa()
407 ADD2(res8, out8, res9, out9, res8, res9); in vpx_iadst16_1d_columns_addblk_msa()
408 CLIP_SH2_0_255(res8, res9); in vpx_iadst16_1d_columns_addblk_msa()
409 PCKEV_B2_SH(res8, res8, res9, res9, res8, res9); in vpx_iadst16_1d_columns_addblk_msa()
411 ST8x1_UB(res9, dst + 14 * dst_stride); in vpx_iadst16_1d_columns_addblk_msa()
/external/llvm/test/Bitcode/
DmiscInstructions.3.2.ll99 ; CHECK-NEXT: %res9 = icmp slt i32 %x1, %x2
100 %res9 = icmp slt i32 %x1, %x2
141 ; CHECK-NEXT: %res9 = fcmp olt float %x1, %x2
142 %res9 = fcmp olt float %x1, %x2
DmemInstructions.3.2.ll54 ; CHECK-NEXT: %res9 = load i8, i8* %ptr1, !invariant.load !1
55 %res9 = load i8, i8* %ptr1, !invariant.load !1
110 ; CHECK-NEXT: %res9 = load atomic i8, i8* %ptr1 singlethread unordered, align 1
111 %res9 = load atomic i8, i8* %ptr1 singlethread unordered, align 1
262 ; CHECK-NEXT: %res9 = extractvalue { i32, i1 } [[TMP]], 0
263 %res9 = cmpxchg i32* %ptr, i32 %cmp, i32 %new release monotonic
/external/llvm/test/CodeGen/AMDGPU/
Dllvm.SI.resinfo.ll31 %res9 = call <4 x i32> @llvm.SI.resinfo(i32 %a9, <32 x i8> undef, i32 9)
55 %t8 = extractelement <4 x i32> %res9, i32 1
56 %t9 = extractelement <4 x i32> %res9, i32 3
Dllvm.AMDGPU.tex.ll30 %res9 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %res8, i32 0, i32 0, i32 9)
31 %res10 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %res9, i32 0, i32 0, i32 10)
Dllvm.SI.sampled.ll54 %res9 = call <4 x float> @llvm.SI.sampled.(<4 x i32> %v9,
86 %t8 = extractelement <4 x float> %res9, i32 1
87 %t9 = extractelement <4 x float> %res9, i32 3
Dllvm.SI.sample.ll54 %res9 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v9,
86 %t8 = extractelement <4 x float> %res9, i32 1
87 %t9 = extractelement <4 x float> %res9, i32 3
Dfetch-limits.r700+.ll47 %res9 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %9, i32 0, i32 0, i32 1)
59 %e = fadd <4 x float> %res8, %res9
/external/clang/test/SemaCXX/
Daltivec.cpp28 int res9[vec_step(vbi) == 4 ? 1 : -1]; in test_vec_step() local
/external/llvm/test/CodeGen/ARM/
Dintrinsics-crypto.ll39 %res9 = call <4 x i32> @llvm.arm.neon.sha256su1(<4 x i32> %res8, <4 x i32> %tmp3, <4 x i32> %res1)
41 %res10 = call <4 x i32> @llvm.arm.neon.sha256su0(<4 x i32> %res9, <4 x i32> %tmp3)
/external/clang/test/SemaOpenCL/
Dvec_step.cl24 int res9[vec_step(int4) == 4 ? 1 : -1];