| /external/valgrind/VEX/priv/ |
| D | host_generic_reg_alloc2.c | 79 HReg rreg; member
745 rreg_lrs_la[rreg_lrs_used].rreg = univ->regs[j]; in doRegisterAllocation()
782 rreg_lrs_la[rreg_lrs_used].rreg = univ->regs[j]; in doRegisterAllocation()
797 HReg rreg = rreg_lrs_la[j].rreg; in doRegisterAllocation() local
798 vassert(!hregIsVirtual(rreg)); in doRegisterAllocation()
801 UInt ix = hregIndex(rreg); in doRegisterAllocation()
845 (*ppReg)(rreg_lrs_la[j].rreg); in doRegisterAllocation()
852 (*ppReg)(rreg_lrs_db[j].rreg); in doRegisterAllocation()
1016 HReg reg = rreg_lrs_la[j].rreg; in doRegisterAllocation()
1044 HReg reg = rreg_lrs_la[k].rreg; in doRegisterAllocation()
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| D | host_tilegx_defs.c | 1201 void genSpill_TILEGX ( /*OUT*/ HInstr ** i1, /*OUT*/ HInstr ** i2, HReg rreg, in genSpill_TILEGX() argument
1206 vassert(!hregIsVirtual(rreg)); in genSpill_TILEGX()
1210 switch (hregClass(rreg)) { in genSpill_TILEGX()
1212 *i1 = TILEGXInstr_Store(8, am, rreg); in genSpill_TILEGX()
1215 *i1 = TILEGXInstr_Store(4, am, rreg); in genSpill_TILEGX()
1218 ppHRegClass(hregClass(rreg)); in genSpill_TILEGX()
1223 void genReload_TILEGX ( /*OUT*/ HInstr ** i1, /*OUT*/ HInstr ** i2, HReg rreg, in genReload_TILEGX() argument
1227 vassert(!hregIsVirtual(rreg)); in genReload_TILEGX()
1230 switch (hregClass(rreg)) { in genReload_TILEGX()
1232 *i1 = TILEGXInstr_Load(8, rreg, am); in genReload_TILEGX()
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| D | host_mips_defs.c | 1971 void genSpill_MIPS( /*OUT*/ HInstr ** i1, /*OUT*/ HInstr ** i2, HReg rreg, in genSpill_MIPS() argument
1976 vassert(!hregIsVirtual(rreg)); in genSpill_MIPS()
1980 switch (hregClass(rreg)) { in genSpill_MIPS()
1983 *i1 = MIPSInstr_Store(8, am, rreg, mode64); in genSpill_MIPS()
1987 *i1 = MIPSInstr_Store(4, am, rreg, mode64); in genSpill_MIPS()
1991 *i1 = MIPSInstr_FpLdSt(False /*Store */ , 4, rreg, am); in genSpill_MIPS()
1994 *i1 = MIPSInstr_FpLdSt(False /*Store */ , 8, rreg, am); in genSpill_MIPS()
1997 ppHRegClass(hregClass(rreg)); in genSpill_MIPS()
2003 void genReload_MIPS( /*OUT*/ HInstr ** i1, /*OUT*/ HInstr ** i2, HReg rreg, in genReload_MIPS() argument
2007 vassert(!hregIsVirtual(rreg)); in genReload_MIPS()
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| D | host_x86_defs.c | 1706 HReg rreg, Int offsetB, Bool mode64 ) in genSpill_X86() argument
1710 vassert(!hregIsVirtual(rreg)); in genSpill_X86()
1714 switch (hregClass(rreg)) { in genSpill_X86()
1716 *i1 = X86Instr_Alu32M ( Xalu_MOV, X86RI_Reg(rreg), am ); in genSpill_X86()
1719 *i1 = X86Instr_FpLdSt ( False/*store*/, 10, rreg, am ); in genSpill_X86()
1722 *i1 = X86Instr_SseLdSt ( False/*store*/, rreg, am ); in genSpill_X86()
1725 ppHRegClass(hregClass(rreg)); in genSpill_X86()
1731 HReg rreg, Int offsetB, Bool mode64 ) in genReload_X86() argument
1735 vassert(!hregIsVirtual(rreg)); in genReload_X86()
1739 switch (hregClass(rreg)) { in genReload_X86()
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| D | host_tilegx_defs.h | 529 HReg rreg, Int offset );
531 HReg rreg, Int offset );
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| D | host_x86_defs.h | 730 HReg rreg, Int offset, Bool );
732 HReg rreg, Int offset, Bool );
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| D | host_amd64_defs.h | 801 HReg rreg, Int offset, Bool );
803 HReg rreg, Int offset, Bool );
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| D | host_mips_defs.h | 697 HReg rreg, Int offset, Bool);
699 HReg rreg, Int offset, Bool);
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| D | host_arm_defs.h | 1040 HReg rreg, Int offset, Bool );
1042 HReg rreg, Int offset, Bool );
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| D | host_amd64_defs.c | 1955 HReg rreg, Int offsetB, Bool mode64 ) in genSpill_AMD64() argument
1959 vassert(!hregIsVirtual(rreg)); in genSpill_AMD64()
1963 switch (hregClass(rreg)) { in genSpill_AMD64()
1965 *i1 = AMD64Instr_Alu64M ( Aalu_MOV, AMD64RI_Reg(rreg), am ); in genSpill_AMD64()
1968 *i1 = AMD64Instr_SseLdSt ( False/*store*/, 16, rreg, am ); in genSpill_AMD64()
1971 ppHRegClass(hregClass(rreg)); in genSpill_AMD64()
1977 HReg rreg, Int offsetB, Bool mode64 ) in genReload_AMD64() argument
1981 vassert(!hregIsVirtual(rreg)); in genReload_AMD64()
1985 switch (hregClass(rreg)) { in genReload_AMD64()
1987 *i1 = AMD64Instr_Alu64R ( Aalu_MOV, AMD64RMI_Mem(am), rreg ); in genReload_AMD64()
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| D | host_arm_defs.c | 2557 HReg rreg, Int offsetB, Bool mode64 ) in genSpill_ARM() argument
2561 vassert(!hregIsVirtual(rreg)); in genSpill_ARM()
2564 rclass = hregClass(rreg); in genSpill_ARM()
2569 rreg, in genSpill_ARM()
2589 rreg, in genSpill_ARM()
2593 rreg, in genSpill_ARM()
2602 *i2 = ARMInstr_NLdStQ(False, rreg, mkARMAModeN_R(r12)); in genSpill_ARM()
2612 HReg rreg, Int offsetB, Bool mode64 ) in genReload_ARM() argument
2616 vassert(!hregIsVirtual(rreg)); in genReload_ARM()
2619 rclass = hregClass(rreg); in genReload_ARM()
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| D | host_arm64_defs.h | 974 HReg rreg, Int offset, Bool );
976 HReg rreg, Int offset, Bool );
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| D | host_ppc_defs.c | 2995 HReg rreg, Int offsetB, Bool mode64 ) in genSpill_PPC() argument
2998 vassert(!hregIsVirtual(rreg)); in genSpill_PPC()
3001 switch (hregClass(rreg)) { in genSpill_PPC()
3004 *i1 = PPCInstr_Store( 8, am, rreg, mode64 ); in genSpill_PPC()
3008 *i1 = PPCInstr_Store( 4, am, rreg, mode64 ); in genSpill_PPC()
3011 *i1 = PPCInstr_FpLdSt ( False/*store*/, 8, rreg, am ); in genSpill_PPC()
3016 *i1 = PPCInstr_AvLdSt ( False/*store*/, 16, rreg, am ); in genSpill_PPC()
3019 ppHRegClass(hregClass(rreg)); in genSpill_PPC()
3025 HReg rreg, Int offsetB, Bool mode64 ) in genReload_PPC() argument
3028 vassert(!hregIsVirtual(rreg)); in genReload_PPC()
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| D | host_arm64_defs.c | 2505 HReg rreg, Int offsetB, Bool mode64 ) in genSpill_ARM64() argument
2509 vassert(!hregIsVirtual(rreg)); in genSpill_ARM64()
2512 rclass = hregClass(rreg); in genSpill_ARM64()
2520 rreg, in genSpill_ARM64()
2528 rreg, hregARM64_X21(), offsetB); in genSpill_ARM64()
2536 *i2 = ARM64Instr_VLdStQ(False/*!isLoad*/, rreg, x9); in genSpill_ARM64()
2546 HReg rreg, Int offsetB, Bool mode64 ) in genReload_ARM64() argument
2550 vassert(!hregIsVirtual(rreg)); in genReload_ARM64()
2553 rclass = hregClass(rreg); in genReload_ARM64()
2561 rreg, in genReload_ARM64()
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| D | host_ppc_defs.h | 1124 HReg rreg, Int offsetB, Bool mode64 );
1126 HReg rreg, Int offsetB, Bool mode64 );
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| D | host_s390_defs.c | 470 genSpill_S390(HInstr **i1, HInstr **i2, HReg rreg, Int offsetB, Bool mode64) in genSpill_S390() argument
475 vassert(!hregIsVirtual(rreg)); in genSpill_S390()
481 switch (hregClass(rreg)) { in genSpill_S390()
484 *i1 = s390_insn_store(8, am, rreg); in genSpill_S390()
488 ppHRegClass(hregClass(rreg)); in genSpill_S390()
496 genReload_S390(HInstr **i1, HInstr **i2, HReg rreg, Int offsetB, Bool mode64) in genReload_S390() argument
501 vassert(!hregIsVirtual(rreg)); in genReload_S390()
507 switch (hregClass(rreg)) { in genReload_S390()
510 *i1 = s390_insn_load(8, rreg, am); in genReload_S390()
514 ppHRegClass(hregClass(rreg)); in genReload_S390()
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